SAA32M4 Datasheet, PDF (1/13 Pages) List of Unclassifed Manufacturers – DOUBLE DATA RATE (DDR) SDRAM

128Mb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
Timing – Cycle Time
(DDR) SDRAM
7.5ns @ CL = 2.5 (PC2100)
10ns @ CL = 2.5 (PC1600)
-75A
-8A
• PC1600 and PC2100 compatible
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
Part number example: SAA16M8T95AV4TL-75A
(For part numbers prior to December
2004, refer to page 13 for decoding.)
• Bi-directional data strobe (DQS) transmitted/ received with
data, i.e., source-synchronous data capture (x16 has two –
one per byte)
• Internal, pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two –
one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
Options:
Family
SpecTek Memory
Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
Design ID
DDR 128 Megabit Design
(Call SpecTek Sales for details on
availability of “x” placeholders)
Voltage and refresh
2.5V, Auto Refresh
2.5V, Self or Auto Refresh
Plastic Package – OCPL
66-pin TSOP
(400 mil width, 0.65mm pin pitch)
Designation:
SAA
32M4
16M8
8M16
Yx6x
V4
R4
TL
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
1
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