PLL650-02 Datasheet, PDF (1/6 Pages) List of Unclassifed Manufacturers – Low EMI Network LAN Clock

FEATURES
• Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
• Advanced, low power, sub-micron CMOS processes.
• 25MHz fundamental crystal or clock input.
• 4 outputs at 50MHz, 2 outputs selectable at 25MHz or
125MHz, 1 output selectable at 25MHz or 100MHz.
• 2 SDRAM selectable frequencies of 66.6, 75, 83.3,
100MHz (Double Drive Strength).
• All non SDRAM outputs can be disabled (tri-state)
• Spread spectrum technology selectable for EMI
reduction from ±0.5%, ±0.75% for SDRAM and 100MHz
output.
• Zero PPM synthesis error in all clocks.
• Ideal for Network switches.
• 3.3V operation.
• Available in 24-Pin 150mil SSOP.
DESCRIPTIONS
The PLL 650-02 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25 MHz crystal, and produces multiple output
clocks for networking chips, PCI devices, SDRAM, and
ASICs, with double drive strength for its SDRAM outputs.
BLOCK DIAGRAM
PLL650-02
Low EMI Network LAN Clock
PIN CONFIGURATION
VDD 1
XIN 2
XOUT/50MHz_OE*^ 3
GND 4
VDD 5
50MHz/FS0*^ 6
GND ⁷
50MHz/FS1*^ ⁸
50MHz/FS2*^T 9
FS3^T 10
50MHz/SS0*^T 11
VDD 12
24 VDD
23 VDD
22 25MHz/100MHz
21 GND
20 SDRAMx2
19 GND
18 SDRAMx2
17 VDD
16 VDD
15 25MHz/125MHz
14 GND
13 25MHz/125MHz
Note: SDRAMx2: Double Drive strength. ^T: Tri-Level input ^{^}: Internal pull-up
resistor. *: Bi-directional pin (input value is latched upon power-up).
FREQUENCY TABLE
FS1 FS0
0
0
0
1
1
0
1
1
SDRAM
100MHz^SST
75MHz^SST
83.3MHz^SST
66.6MHz^SST
FS3 Pin 13, 15 FS2
Pin 22
0
Disable
0
25MHz
M
125MHz
M
Disable
1
25MHz
1
100MHz^SST
FS(2:3): Tri-level inputs.
SST: SST modulation applied (see selection table)
XIN
XOUT
XTAL
OSC
FS (0:3)
Control
Logic
4
50MHz
(can be disabled)
2
25MHz/125MHz
(can be disabled)
2
SDRAM (66.6, 75, 83.3, 100MHz)
1
25MHz/100MHz
(can be disabled)
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Rev 05/02/01 Page 1