MX98725 Datasheet, PDF (1/33 Pages) List of Unclassifed Manufacturers – SINGLE CHIP FAST ETHERNET NIC CONTROLLER

PRELIMINARY
MX98725
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
1. FEATURES
• A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
• Fully comply to IEEE 802.3u specification
• Operates over 100 meters of STP and category 5
UTP cable
• Support full and half duplex operation in both 100
Base-TX and 10 Base-T mode
• Fully comply to PCI spec. 2.1 with bus clock ranges
from 16MHz to 33MHz
• Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.0
• Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.0
• Magic Packet TM mode to support Remote-Power
On and Remote-Wake-Up.
• 100/10 Base-T NWAY auto negotiation function
• Large on chip FIFOs for both transmit and receive
operations without external local memory
• Bus master architecture with linked host buffers
delivers the most optimized performance
• 32-bit bus master DMA channel provides ultra low
CPU utilization
• Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
• Support up to 256K bytes boot ROM and FLASH
interface
• Three levels of loopback diagnostic capability
• Support a variety of flexible address filtering modes
with 16 CAM address and 512 bits hash
• MicroWire interface to EEPROM for customer's IDs
and configuration data
• Single +5.0V power supply, standard CMOS tech-
nology, 160 pin PQFP package
( Magic Packet technology is a trademark of Advanced
Micro Device Corp.)
2. GENERAL DESCRIPTIONS
The MX98725, second generation of 100/10 Base-T
single chip MAC controller, is designed specifically to
meet future demand on Fast Ethernet networking sys-
tem. Different from MX98715/715a3, MX98725 addition-
ally supports ACPI, Remote-Wake-Up, Remote-Power-
On, and up to 256K Bytes Flash interface to enhance
product's added-on value.
The MX9725 controller is an IEEE802.3u compliant
single chip 32-bit full duplex, 10/100Mbps highly inte-
grated Fast Ethernet combo solution, designed to ad-
dress high performance local area networking (LAN)
system application requirements.
The bus master architecture delivers the performance
needed for today high speed and powerful processors
technology. In other words, the MX98725 not only keeps
CPU utilization low while maximizing data throughput,
but it also optimizes the PCI bandwidth providing the
highest PCI bandwidth utilization. To further reduce
ownership costs the MX98725 uses drivers that are
backward-compatible with the original MXIC MX98713
series controllers.
The MX98725 contains a PCI local bus glueless inter-
face, a Direct Memory Access (DMA) buffer manage-
ment unit, an IEEE802.3u-compliant Media Access Con-
troller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98725-based adapter allows a single
RJ-45 connector to link with the other IEEE802.3u-com-
pliant device completely without any need to set con-
figuration.
In MX98725, an innovative and proprietary design
"Adaptive Network Throughput Control" (ANTC) is built-
in to configure itself automatically by MXIC's driver based
on the PCI burst throughput of different PCs. With this
proprietary design, MX98725 can always optimize its
operating bandwidth, network data integrity and through-
put for different PCs.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
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