MX802 Datasheet, PDF (1/24 Pages) List of Unclassifed Manufacturers – DVSR CODEC

DATA BULLETIN
MX802
DVSR CODEC
Features
 DVSR (Data/Voice Storage and Retrieval)
Codec
 CVSD Codec Encoder and Decoder
 Control and Timing Circuitry for 4Mbits
of external DRAM
 Low Power Operation
 Member of DBS800 Family (C-BUS
Compatible)
Applications
 Answering Machines where an incoming
speech message is stored for later recall
 Busy Buffering, in which an outgoing
speech message is stored temporarily
 Automatic transmission of pre-recorded
alarm or status messages.
 Time Domain Scrambling of Speech
messages
 VOX control of transmitter functions
 Temporary Data Storage, such as
buffering of over-air data transmissions
SERIAL
COMMAND
REPLY
CS
CLOCK
DATA
DATA
IRQ
XTAL/ XTAL
AUDIO
CLOCK
IN
AUDIO
OUT
C-BUS INTERFACE AND CONTROL LOGIC
CLOCK
GENERATOR
PLAY
COMMAND
BUFFER
STORE
COMMAND
BUFFER
CONTROL
REGISTER
STATUS
REGISTER
DATA
READ
COUNTER
DATA
WRITE
COUNTER
SPEECH
PLAY
COUNTERS
SPEECH
STORE
COUNTERS
POWER
ASSESS
ENCODER DECODER
CLOCK CLOCK
ENCODE
CLOCK
MOD
DECODE
CLOCK
IDLE
PATTERN
DEMOD
DRAM CONTROL AND TIMING
DIRECT ACCESS CLOCKS AND DATA
WE CAS RAS1 RAS2 RAS3 RAS4
DRAM Data In/ DRAM Data Out/
A0/ENO
A1/DEI
A9 A8 A7 A6 A5 A4 A3/ECK A2/DCK (ENCODER
(DECODER
OUT)
IN)
DRAM ADDRESS LINES
V_DD
V_BIAS V_SS
The MX802 Data/Voice Storage and Retrieval (DVSR) Codec contains a Continuously Variable Slope Delta
Modulation (CVSD) encoder and decoder as well as control and timing circuitry for up to 4Mbits of external
DRAM. As a member of the DBS800 series, it also contains interface and control logic for the “C-BUS” serial
interface.
When used with external DRAM, theMX802 had four primary functions: Speech Storage, Speech layback,
Data Storage, and Data Retrieval. The Speech Storage and Playback may be performed concurrently with
data storage or retrieval.
On-chip the Delta Codec is supported by input and output analog switched-capacitor filters and audio output
switching circuitry. The DRAM control and timing circuitry provides all the necessary address, control, and
refresh signals to interface to external DRAM.
The MX802 may also be used without DRAM (as a “stand alone” CVSD Codec), in which case direct access
is provided to the CVSD Codec digital data and clock signals. All signals are controlled by “C-BUS”
commands from the system microcontroller.
The MX802 may be used with a 5.0V power supply and is available in the following packages:
24-pin PLCC (MX802LH), 28-pin PLCC (MX802LH8), and 28-pin PDIP (MX802P).

1998 MX-COM, Inc.
www.mxcom.com Tel: [phone] 744 5050 Fax: [phone]
Doc. # 20480033.008
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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