LD4000 Datasheet, PDF (1/4 Pages) List of Unclassifed Manufacturers – PR4/EPR4 Read/Write Controller

LD4000
PR4/EPR4 Read/Write Controller
GENERAL DESCRIPTION
The part is a high performance BICMOS read channel IC that provides all of the functions needed to
implement an entire Partial Response Class 4 (PR4) read channel for zoned recording hard disk drive
systems with data rates from 67 to 212 Mbps.
Functional blocks include a serial port, an automatic gain control amplifier, a programmable filter, an
offset canceller, a peak detecting pulse qualifier, an adaptive transversal filter, a Viterbi qualifier, a 8/9
GCR ENDEC, a data synchronizer, a time base generator, an integrating servo demodulator, as shown in
figure 1.
The part requires a single +5V power supply. The part utilizes an advanced BiCMOS process technology
along with advanced circuit design techniques which results in a high performance device with low power
consumption.
FEATURES
GENERAL
• Register programmable data rates from 67 to
212 Mbit/s
• Sampled data read channel with Viterbi
qualification
• Programmable filter for PR4 equalization
• Five tap transversal filter with adaptive PR4
equalization
• 8/9 GCR ENDEC
• Data Scrambler / Descrambler
• Presettable Precoder state
• Programmable write precompensation
• Low operating power - 1000mW maximum
at 5.5V to allow use of TOFP packages.
Active power management is applied to
achieve this target
• Register programmable power management
(<5 mW power down mode)
• 4-bit nibble and byte wide bi-directional
NRZ data interface
• 8 bit direct write mode automatically
configured for CLK=VCO/8
• Serial Interface port for access to internal
program storage registers
• Single power supply (5V ± 10%)
• Small package footprint: 100 lead TOFP
AUTOMATIC GAIN CONTROL
• Dual mode AGC, continuous time during
acquisition, sampled during data reads
• Separate AGC level storage pins for data and
servo
• Dual rate attack and decay charge pump for
rapid AGC recovery in continuous time mode
• Programmable, symmetric, charge pump
currents for data reads in sampled mode
• Charge pump currents track programmable
data rate during data reads
• Low drift AGC hold circuitry
• Low-Z circuitry at AGC input provides for
rapid external coupling capacitor recovery
• AGC Amplifier squelch during Low-Z
• Wide bandwidth amplitude feedback circuit
to allow improved stability of AGC level vs.
frequency
• Programmable AGC controls
• Separate external input pins for AGC
hold, fast recovery, and Low-Z control
or
• Internal Low-Z and fast recovery timing
for rapid transient recovery and AGC
acquisition. Timing set with external
resistors (2). Ultra fast decay current set
with external resistor.
version 2.1