CH7013B Datasheet, PDF (1/46 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

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Digital PC to TV Encoder
CH7013B
1. FEATURES
• Universal digital interface accepts YCrCb (CCIR601
or 656) or RGB (15, 16 or 24-bit) video data in both
non-interlaced and interlaced formats
• True scale rendering engine supports underscan
operations for various graphics resolutions
• Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering
• Enhanced dot crawl control and area reduction
• Fully programmable through serial port
• Supports NTSC, NTSC-J, and PAL (B, D, G, H, I, M
and N) TV formats
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
• Supports VBI pass-through
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in 48-pin LQFP
2. GENERAL DESCRIPTION
Chrontel’s CH7013B digital PC to TV encoder is a stand-
alone integrated circuit providing a robust solution for TV
output. It provides a universal digital input port to accept a
pixel data stream from a compatible VGA controller (or
equivalent) and converts it directly into the NTSC or PAL
TV format.
This device integrates a digital NTSC/PAL encoder with a 9-
bit DAC interface, an adaptive flicker filter, and a high
accuracy low-jitter phase locked loop to create outstanding
quality video. Through its true scale scaling and de-
flickering engine, the CH7013B supports full vertical and
horizontal underscan capability and operates in 5 different
resolutions including 640x480 and 800x600.
A universal digital interface along with full programmability
make the CH7013B ideal for system-level PC solutions. All
features are software programmable through a serial port to
enable a complete PC solution using a TV as the primary
display.
LINE
MEMORY
YUV-RGB CONVERTER
D[15:0]
PIXEL DATA
DIGITAL
INPUT
INTERFACE
RGB-YUV
CONVERTER
TRUE SCALE
SCALING & DEFLICKERING
ENGINE
NTSC/PAL
ENCODER
& FILTERS
TRIPLE
DAC
SYSTEM CLOCK
SERIAL CONTROL BLOCK
PLL
TIMING & SYNC GENERATOR
CLOCK
DATA
ADDR
XCLK
H
V XI XO/FIN CSYNC P-OUT BCO
Figure 1: Functional Block Diagram
Y/R
C/G
CVBS/B
RSET
201-0000-069 Rev. 1.2, 9/1/2004
1