AN103 Datasheet, PDF (1/5 Pages) List of Unclassifed Manufacturers – The FET Constant-Current Source/Limiter

The FET Constant-Current Source/Limiter
AN103
Introduction
The combination of low associated operating voltage and
high output impedance makes the FET attractive as a
constant-current source. An adjustable-current source (Fig-
ure 1) may be built with a FET, a variable resistor, and a
small battery. For optimum thermal stability, the FET should
be biased near the zero temperature coefficient point.
D
S
R_L
R_S
–+
A change in supply voltage or a change in load imped-
ance, will change I_D by only a small factor because of the
low output conductance g_oss.
DI_D = (DV_DS)(g_oss)
(3)
The value of g_oss is an important consideration in the ac-
curacy of a constant-current source where the supply volt-
age may vary. As g_oss may range from less than 1 mS to
more than 50 mS according to the FET type, the dynamic
impedance can be greater than 1 MW to less than 20 kW.
This corresponds to a current stability range of 1 mA to
50 mA per volt. The value of g_oss also depends on the op-
erating point. Output conductance g_oss decrease approxi-
mately linearly with I_D. The relationship is
I_D
I_DSS
+
g_oss
gȀ_oss
(4)
Figure 1. Field-Effect Transistor Current Source
NO TAG
where g_oss = gȀ_oss
(5)
Whenever the FET is operated in the current saturated re-
gion, its output conductance is very low. This occurs
whenever the drain-source voltage V_DS is at least 50%
greater than the cut-off voltage V_GS(off). The FET may be
biased to operate as a constant-current source at any cur-
rent below its saturation current I_DSS.
Basic Source Biasing
For a given device where I_DSS and V_GS(off) are known, the
approximate V_GS required for a given I_D is
ƪ ^{ǒ Ǔ} ƫ V_GS + V_GS(off)
1ńk
1–
I_D
I_DSS
(1)
where k can vary from 1.8 to 2.0, depending on device ge-
ometry. If K = 2.0, the series resistor R_S required between
source and gate is
R_S
+
V_GS
I_D
ǒ Ǹ Ǔ ^or
R_S
+
V_GS(off)
I_D
1–
I_D
I_DSS
(2)
when V_GS = 0
(6)
So as V_GS → V_GS(off), g_oss → Zero. For best regulation,
I_D must be considerably less than I_DSS.
Cascading for Low g_oss
It is possible to achieve much lower g_oss per unit I_D by
cascading two FETs, as shown in Figure 2.
D
Q₁
S
SD
Q₂
R_L
R_S
–
+
V_DD
Figure 2. Cascade FET Current Source
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Siliconix
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10-Mar-97