AMP374P6453BT1C1H Datasheet, PDF (1/12 Pages) List of Unclassifed Manufacturers – 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs

AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
DESCRIPTION
AVED Memory Products AMP374P6453BT1-C1H/S is a 64M bit X 72 Synchronous Dynamic RAM high density
memory module. The AVED Memory Products AMP374P6453BT1-C1H/S consists of eighteen CMOS 32M X 8 bit
with 4 banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a
168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM.
The AVED Memory Products AMP374P6453BT1-C1H/S is a Dual In-Line Memory Module and is intended for mount-
ing into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system
clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies
allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
APPLICATION
Main Memory unit for computer, Microcomputer memory,
Refresh memory for CRT.
FEATURES
• Performance Ranges
• Part Identification
- AMP374P6453BT1-C1H/S
8k cycles/64ms Ref, TSOP, Gold Contact Plating
- PC100 Compliant
Part #
Maximum Frequency/Speed
AMP374P6453BT1-C1H/S PC100MHz (10ns @ CL=2)
• Burst Mode Operation
• Auto & Self Refresh capability (8k cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V _± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst Length (1, 2, 4, 8 & Full Page)
Data Scramble (Sequential & Interleave)
• All inputs are sampled at the positive
going edge of the system clock
• Serial Presence Detect with EEPROM
PIN NAMES
Pin Nam e
A0 - A12
BA0 - BA1
DQ0 - DQ63
CB0 - 7
CLK0 - CLK3
CKE0 - CKE1
CS0 - CS3
RAS
CAS
WE
DQM0 - 7
VDD
Vss
*VREF
SDA
SCL
SA0 - 2
WP
DU
NC
Function
Address Input (multiplexed)
Select Bank
Data Input/Output
Check Bit (Data-in/out)
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
W rite Enable
DQM
Power Supply(3.3V)
G ro u n d
Power Supply for Reference
Serial Address Data I/O
Serial Clock
Address in EEPROM
W rite Protect
Don’t Use
No Connection
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 1 of 12