MC80F0424 Datasheet, PDF (94/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0424/0432/0448
Preliminary
19. INTERRUPTS
The MC80F0424/0432/0448 interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flags of IRQH,
IRQL, Priority circuit, and Master enable flag (“I” flag of PSW).
Fifteen interrupt sources are provided. The configuration of inter-
rupt circuit is shown in Figure 19-1 and interrupt priority is
shown in Table 19-1.
The External Interrupts INT0 ~ INT3 each can be transition-acti-
vated (1-to-0 or 0-to-1 transition) by selection IEDS register.
The flags that actually generate these interrupts are bit INT0IF,
INT1IF, INT2IF and INT3IF in register IRQH. When an external
interrupt is generated, the generated flag is cleared by the hard-
ware when the service routine is vectored to only if the interrupt
was transition-activated.
The Timer 0 ~ Timer 4 Interrupts are generated by T0IF, T1IF,
T2IF, T3IF and T4IF which is set by a match in their respective
timer/counter register.
The Basic Interval Timer Interrupt is generated by BITIF which
is set by an overflow in the timer register.
The AD converter Interrupt is generated by ADCIF which is set
by finishing the analog to digital conversion.
The Watchdog timer and Watch Timer Interrupt is generated by
WDTIF and WTIF which is set by a match in Watchdog timer
register or Watch timer register. The IFR(Interrupt Flag Register)
is used for discrimination of the interrupt source among these two
Watchdog timer and Watch Timer Interrupt.
The Basic Interval Timer Interrupt is generated by BITIF which
is set by a overflow in the timer counter register.
INT0
INT1
INT2
INT3
UART0 Tx/Rx
UART1 Tx/Rxt
Serial
Communication
Timer 0
Timer 1
Timer 2
Timer 3
Timer 3
A/D Converter
Watchdog Timer
Watch Timer
BIT
Internal bus line
IRQH
[0EC_H]
INT0IF
INT1IF
INT2IF
INT3IF
UART0IF
UART1IF
SIOIF
IRQL
[0ED_H]
T0IF
T1IF
T2IF
T3IF
T4IF
ADCIF
WDTIF
WTIF
BITIF
[0EA_H]
IENH
Interrupt Enable
Register (Higher byte)
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
Release STOP/SLEEP
I-flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
To CPU
[0EB_H]
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 19-1 Block Diagram of Interrupt
90
MAR. 2005 Ver 0.2