TM133XG-02L07 Datasheet, PDF (9/16 Pages) List of Unclassifed Manufacturers – ETFT COLOR LCD MODULE

INTERFACE (LVDS) SIGNAL TIMING PARAMETERS
PARAMETER
Data Setup Time
Data Hold Time
SYMBOL MIN
tsu
600
thd
600
TYP
-
-
MAX
-
-
UNIT
ps
ps
NOTE
at Tin=15ns
Note 1
[Note 1] In the following timing waveform, the n-th edge of internal imaginary clock tcn,
which is sampling position of LVDS input data signal, is given by:
tcn = (2n-1) Tin / 14
(n=1,2, ~ 7)
where Tin is period of LVDS input clock.
For this imaginary clock edge, data setup time is tsu and data hold time is thd,
respectively.
Tin
tcn
LVDS Input Clock
tsu
LVDS Input Data
thd
n-th edge of internal imaginary clock (data sampling position)
CYCLE JITTER of LVDS CLOCK
PARAMETER
SYMBOL MIN
P-P of jitter / 100 cycles tcj1
-
Jitter rate
tcj2
-
TYP
-
-
MAX
300
20
UNIT
ps
ps/cycle
NOTE
Note 1
[Note 1] Please confirm tcj2 (Jitter rate), only if tcj1 (P-P of jitter/100cycles) exceeds 300ps.
[Additional explanation]
Right diagram shows the example of
CYCLE JITTER of LVDS CLOCK.
According to this diagram, tCLK MIN. is
15.0ns and tCLK MAX. is 15.42ns between
0cycle and 100cycles. The tcj1 (P-P of jitter /
100 cycles) in this sphere is
tcj1=15.42-15.0=0.42 ns
and out of specification (300ps MAX.).
So, it is neccesary to measure tcj2 (jitter rate)
and to judge whether it conform to above
specification.
According to the diagram, the sharpest
fluctuation of tCLK is 0.4ns per 5cycles. So
that, the tcj2 in this sphere is
15.6
15.5
15.4
15.3
15.2
15.1
15.0
14.9
0
<EXAMPLE>
CYCLE JITTER of LVDS CLOCK
50 100 150 200 250
Cycle nc (n)
tcj2=0.4/5=0.08 ns/cycle
and larger than specification (20ps/cycle MAX.).
In conclusion, normal function of the LCD module can not be assured in this case.
Tottori SANYO Electric Co., Ltd. TM133XG-02L07 Ver.2 Page 8/16