LM3S815_06 Datasheet, PDF (89/412 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S815 Data Sheet
Register 22: Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104
Register 23: Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114
Register 24: Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will
generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that
all functional units are disabled. It is the responsibility of software to enable the ports necessary for
the application. Note that these registers may contain more bits than there are interfaces,
functions, or units to control. This is to assure reasonable code compatibility with other family and
future parts.
RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and
DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 81) specifies that the system uses sleep modes.
Run-Mode, Sleep-Mode, and Deep-Sleep-Mode Clock Gating Control 1 (RCGC1, SCGC1, and DCGC1)
Offset 0x104, 0x114, and 0x124
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Type
RO
Reset
0
15
reserved
RO
RO
RO
0
0
0
14
13
12
COMP2 COMP1 COMP0
RO
R/W
R/W
R/W
RO
0
0
0
0
0
11
10
9
8
7
reserved
RO
RO
RO
0
0
0
6
5
4
GPTM2 GPTM1 GPTM0
RO
R/W
R/W
R/W
0
0
0
0
3
2
1
0
reserved
I2C
reserved
SSI
reserved
UART1 UART0
Type
RO
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
RO
RO
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:27
26
Name
reserved
COMP2
25
COMP1
24
COMP0
23:19
18
reserved
GPTM2
Type
RO
R/W
R/W
R/W
RO
R/W
Reset
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
This bit controls the clock gating for the Comparator 2
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.^a
This bit controls the clock gating for the Comparator 1
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.^a
This bit controls the clock gating for the Comparator 0
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.^a
Reserved bits return an indeterminate value, and should
never be changed.
This bit controls the clock gating for the General Purpose
Timer 2 module. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled.^a
October 8, 2006
89
Preliminary