HMS81C2012A Datasheet, PDF (88/107 Pages) List of Unclassifed Manufacturers – CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver

HMS81C2012A/2020A
20. POWER FAIL PROCESSOR
The HMS81C20xxA has an on-chip power fail detection
circuitry to immunize against power noise. A configura-
tion register, PFDR, can enable or disable the power fail
detect circuitry. Whenever V_DD falls close to or below
power fail voltage for 100ns, the power fail situation may
reset or freeze MCU according to PFDM bit of PFDR. Re-
fer to “7.4 DC Electrical Characteristics for Standard
Pins(5V)” on page 16.
In the in-circuit emulator, power fail function is not imple-
mented and user can not experiment with it. Therefore, af-
ter final development of user program, this function may
be experimented or evaluated.
Note: User can select power fail voltage level according to
PFD0, PFD1 bit of CONFIG register(703F_H) at the OTP
(HMS87C20xxA) but must select the power fail voltage
level to define PFD option of “Mask Order & Verification
Sheet” at the mask chip(HMS81C20xxA).
Because the power fail voltage level of mask chip
(HMS81C20xxA) is determined according to mask option.
Note: If power fail voltage is selected to 3.0V on 3V oper-
ation, MCU is freezed at all the times.
Power FailFunction
Enable/Disable
Level Selection
OTP
PFDIS flag
PFS0 bit
PFS1 bit
MASK
PFDIS flag
Mask option
Table 20-1 Power fail processor
.
PFDR
R/W R/W R/W
7
6
5
4
3
2
1
0
PFDIS PFDM PFS
ADDRESS: 0EF_H
INITIAL VALUE: ---- -100_B
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
Operation Mode
0 : Normal operation regardless of power fail
1 : MCU will be reset by power fail detection
Disable Flag
0: Power fail detection enable
1: Power fail detection disable
Figure 20-1 Power Fail Voltage Detector Register
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SEP. 2004 Ver 2.00