LM3S1958 Datasheet, PDF (87/435 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S1958 Microcontroller
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes. bit was changed to
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31
30
29
28
27
26
25
24
23
22
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
6
MAXADCSPD
reserved HIB
RO
R/W
R/W
R/W
R/W
RO
R/W
0
0
0
0
0
0
0
21
20
RO
RO
0
0
5
4
reserved
RO
RO
0
0
19
RO
0
3
WDT
R/W
0
18
17
16
SARADC0
RO
RO
R/W
0
0
0
2
1
0
reserved
RO
RO
RO
0
0
0
Bit/Field
31:17
16
15:12
11:8
Name
reserved
SARADC0
reserved
MAXADCSPD
Type
RO
R/W
RO
R/W
Reset
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
This bit controls the clock gating for general SAR ADC module 0. If set,
the unit receives a clock and functions. Otherwise, the unit is unclocked
and disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate.You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x3 1M samples/second
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 14, 2007
87
Luminary Micro Confidential-Advance Product Information