LM3S817 Datasheet, PDF (84/379 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S817 Data Sheet
Bit/Field
26:23
Name
SYSDIV
Type
R/W
22
USESYSDIV
R/W
21
reserved
RO
20
USEPWMDIV
R/W
Reset
0xF
0
0
0
Description
System Clock Divisor
Specifies which divisor is used to generate the system clock
from the PLL output (200 MHz).
Binary Divisor
Frequency
Value (BYPASS=1) (BYPASS=0)
0000 reserved
reserved
0001 /2
reserved
0010 /3
reserved
0011 /4
50 MHz
0100 /5
40 MHz
0101 /6
33.33 MHz
0110 /7
28.57 MHz
0111 /8
25 MHz
1000 /9
22.22 MHz
1001 /10
20 MHz
1010 /11
18.18 MHz
1011 /12
16.67 MHz
1100 /13
15.38 MHz
1101 /14
14.29 MHz
1110 /15
13.33 MHz
1111 /16
12.5 MHz (default)
When reading the Run-Mode Clock Configuration (RCC)
register (see page 84), the SYSDIV value is MINSYSDIV if
a lower divider was requested and the PLL is being used.
This lower value is allowed to divide a non-PLL source.
Use the system clock divider as the source for the system
clock. The system clock divider is forced to be used when
the PLL is selected as the source.
Reserved bits return an indeterminate value, and should
never be changed.
Use the PWM clock divider as the source for the PWM
clock.
May 4, 2007
85
Preliminary