VPX3225D Datasheet, PDF (81/92 Pages) List of Unclassifed Manufacturers – Video Pixel Decoders

PRELIMINARY DATA SHEET
VPX 3225D, VPX 3224D
Address
Hex
Number
of Bits
Mode
h’150
12
w
FP-RAM VPX Back-End
Function
Default Name
Formatter
Format Selection
bit [1:0]: Format Selector
0
00: YUV 4:2:2, ITU-R601
01: YUV 4:2:2, ITU-R656
10: YUV 4:2:2, BStream
bit [2]: Shuffler
0
0 Port A = Y, Port B = UV
1 Port A = UV, Port B = Y
bit [3]: Format of VBI-data (in ITU-R656 mode only!)
0
Two possibilities are supported to disable the protected
values 0 and 255:
0 limitation
1 7-bit resolution + odd parity LSB
Note that this selection is applied for lines within the VBI-
window only!
bit [4]: Transmission of VBI-data (in ITU-R656 mode only)
1
0 transmit as normal video data
1 transmit as ancillary data (with ANC-header)
bit [5]: PIXCLK selection
0
Setting this bit activates the half-clock mode, in which
PIXCLK is divided by 2 in order to spread the video data
stream
0 full PIXCLK (normal operation)
1 PIXCLK divided by 2
bit [6]: Disable splitting of text data bytes
0
During normal operation, sliced teletext bytes are splitted
into 2 nibbles and multiplexed to the luminance and
chrominance part. Setting this bit will disable this splitting.
Sliced teletext data will be output directly on the luminance
path. Note that the limitation of luminance data has to be
disabled with bit [8]. The values 0 and 255 will no longer be
protected in the luminance path!
bit [7]: reserved (must be set to zero)
0
bit [8]: Disable limitation of luminance data (see bit [6])
0
0 enabled
1 disabled
bit [9]: Suppress ITU–R656 headers for blank lines
0
bit [10]: Change of ITU–R656 header flags
0
0 change header flags in SAV
1 change header flags in EAV
bit [11]: reserved (must be set to zero)
0
format_sel
format
shuf
range
ancillary
halfclk
splitdis
dislim
hsup
flagdel
Micronas
81