ICS8735-21 Datasheet, PDF (8/15 Pages) List of Unclassifed Manufacturers – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of the ICS8735-21. In this
example, the input is driven by an HCSL driver. The zero delay
buffer is configured to operate at 155.52MHz input and 77.75MHz
output. The logic control pins are configured as follows:
SEL [3:0] = 0101; PLL_SEL = 1
The decoupling capacitors should be physically located near the
power pin. For ICS8735-21.
3.3V
HCSL
VCC
Zo = 50 Ohm
Zo = 50 Ohm
(155.5 MHz)
SEL2
R8
R9
50
50
R1
50
VCC
U1
1
2
3
CLK
nCLK
4
5
6
MR
VCCI
nFB_IN
7 ^FB_IN
8 ^SEL2
9
10
VEE
nQFB
QFB
R2
ICS8735-21
50
RU3 RU4 RU5 RU6 RU7
1K
1K
SP
1K
SP
R3
PLL_SEL
50
SEL0
SEL1
SEL2
SEL3
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
SP = Space (i.e. not intstalled)
VCC=3.3V
SEL[3:0] = 0101,
Divide by 2
nc
SEL1
SEL0
VCCI
PLL_SEL
20
19
18
17
16
15
SEL1
SEL0
VCC
PLL_SEL
VCCA
VCCA ₁₄
SEL3
SEL3 _{13 VCC}
VCCO
Q
nQ
12
11
VCCA
C11
0.01u
R7 VCC
10
C16
10u
Zo = 50 Ohm
Zo = 50 Ohm
(77.75 MHz)
R4
50
+
-
LVPECL_input
R5
50
Bypass capacitors located
near the power pins
R6
50
(U1-4) VCC (U1-17) (U1-13)
C1
0.1uF
C2
0.1uF
C3
0.1uF
FIGURE 4. ICS8735-21 LVPECL BUFFER SCHEMATIC EXAMPLE
ICS8735AM-21
www.icst.com/products/hiperclocks.html
8
REV. D OCTOBER 27, 2003