GP214D Datasheet, PDF (8/15 Pages) List of Unclassifed Manufacturers – 1.4GHz DUAL PLL

GP214D
1.4GHz DUAL PLL
▪ Filter switch control (SW)
SW terminal, for switching time constant of loop filter is controlled by “SW” bit. High lock mode and
normal lock mode can be arbitrarily selected by filter switch control (SW) with the charge pump output
current.
Control Bits
SW
CP1
CP2
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Mode
High Lock
Normal Lock
CRYSTAL OSCILLATOR CIRCUIT (OSCI, OSCO) AND BUFFER OUT (BO)
Reference frequency input is made directly to OSCI (pin 11). Buffer output (BO, pin 9) can be used for the
2^nd mixer input.
REFERENCE COUNTER
When the control bits (GC1, GC2) are “11”, data is transferred from shift register into the OSC R latch
which sets the divide ratio of 12-bit reference counter. The divide ratio is programmed using the bits as
shown in the table below.
LSB
MSB
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10 R11
R12
GC2
“1”
GC1
“1”
Reference Counter
Group Code
Divide ratio: 2×R = 2×(3 to 4095) = 6 to 8190
Divide
Ratio
R12 R11 R10 R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
1
0
0
4095
1
1
1
1
1
1
1
1
1
1
1
1
Version 1.2 (Jan. 2006)
8
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