AK5357 Datasheet, PDF (8/18 Pages) List of Unclassifed Manufacturers – 24 BIT 96 KHZ ADC

ASAHI KASEI
SWITCHING CHARACTERISTICS
(Ta=−40 ∼ 85°C; VA, VD=2.7 ∼ 5.5V; C_L=20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
Pulse Width Low
fCLK
tCLKL
1.024
0.4/fCLK
Pulse Width High
tCLKH 0.4/fCLK
LRCK Frequency
fs
4
Duty Cycle
Slave mode
45
Master mode
Audio Interface Timing
Slave mode
SCLK Period
tSCK
160
SCLK Pulse Width Low
tSCKL
65
Pulse Width High
tSCKH
65
LRCK Edge to SCLK “↑”
(Note 11) tLRSH
30
SCLK “↑” to LRCK Edge
(Note 11) tSHLR
30
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
SCLK “↓” to SDTO
tSSD
Master mode
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
fSCK
dSCK
tMSLR
−20
tSSD
−20
Reset Timing
PDN Pulse Width
(Note 12) ^tPD
150
PDN “↑” to SDTO valid at Slave Mode (Note 13) ^tPDV
PDN “↑” to SDTO valid at Master Mode (Note 13) ^tPDV
typ
50
64fs
50
4132
4129
Note 11. SCLK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK5357 can be reset by bringing the PDN pin = “L”.
Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
[AK5357]
max
Units
36.864
96
55
MHz
ns
ns
kHz
%
%
ns
ns
ns
ns
ns
35
ns
35
ns
Hz
%
20
ns
35
ns
ns
1/fs
1/fs
MS0294-E-00
-8-
2004/02