BC41B143A-DS-003PC Datasheet, PDF (76/94 Pages) List of Unclassifed Manufacturers – BlueCore 4-ROM Plug-n-Go Single Chip Bluetooth v2.0 + EDR System

Device Terminal Descriptions
10.7.9 PCM Configuration
The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 detailed in Table 10.10 and
PSKEY_PCM_LOW_JITTER_CONFIG in Table 10.11. The default for PSKEY_PCM_CONFIG32 is 0x00800000, i.e.,
first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz
PCM_CLK from 4MHz internal clock with no tri-state of PCM_OUT.
Name
-
SLAVE_MODE_EN
SHORT_SYNC_EN
-
SIGN_EXTEND_EN
LSB_FIRST_EN
TX_TRISTATE_EN
TX_TRISTATE_RISING_EDGE_EN
SYNC_SUPPRESS_EN
GCI_MODE_EN
MUTE_EN
48M_PCM_CLK_GEN_EN
LONG_LENGTH_SYNC_EN
-
Bit Position Description
0
Set to 0
0 = master mode with internal generation of PCM_CLK and
PCM_SYNC.
1
1 = slave mode requiring externally generated PCM_CLK
and PCM_SYNC.
0 = long frame sync (rising edge indicates start of frame).
2
1 = short frame sync (falling edge indicates start of frame).
3
Set to 0.
0 = padding of 8 or 13-bit voice sample into a 16-bit slot by
inserting extra LSBs. When padding is selected with 13-bit
4
voice sample, the 3 padding bits are the audio gain setting;
with 8-bit sample the 8 padding bits are zeroes.
1 = sign-extension.
0 = MSB first of transmit and receive voice samples.
5
1 = LSB first of transmit and receive voice samples.
0 = drive PCM_OUT continuously.
6
1 = tri-state PCM_OUT immediately after falling edge of
PCM_CLK in the last bit of an active slot, assuming the next
slot is not active.
0 = tri-state PCM_OUT immediately after falling edge of
PCM_CLK in last bit of an active slot, assuming the next slot
7
is also not active.
1 = tri-state PCM_OUT after rising edge of PCM_CLK.
0 = enable PCM_SYNC output when master.
8
1 = suppress PCM_SYNC whilst keeping PCM_CLK running.
Some CODECS utilise this to enter a low power state.
9
1 = enable GCI mode
10
1 = force PCM_OUT to 0
0 = set PCM_CLK and PCM_SYNC generation via DDS from
internal 4 MHz clock.
11
1 = set PCM_CLK and PCM_SYNC generation via DDS from
internal 48 MHz clock.
0 = set PCM_SYNC length to 8 PCM_CLK cycles.
12
1 = set length to 16 PCM_CLK cycles.
Only applies for long frame sync and with
48M_PCM_CLK_GEN_EN set to 1.
[20:16] Set to 0b00000
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
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