SI3056 Datasheet, PDF (73/102 Pages) Silicon Laboratories – GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT

Si3056
Si3018/19/10
Register 31. DAA Control 3
Bit D7
Name FULL
Type R/W
D6 D5
FOH[1:0]
R/W
D4 D3 D2
OHS2
R/W
D1
FILT
R/W
D0
LVFD
R/W
Reset settings = 0010_0000
Bit Name
Function
7
FULL Full Scale Transmit and Receive Mode (Si3019 line-side device only).
0 = Default.
1 = Transmit/receive full scale.
This bit changes the full scale of the ADC and DAC from 0 min to +3.2 dBm into a 600 Ω load
(or 1 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits (Register 26)
should be set to all 1s to avoid distortion at low loop currents.
6:5 FOH[1:0] Fast Off-Hook Selection.
These bits determine the length of the off-hook counter. The default setting is 128 ms.
00 = 512 ms.
01 = 128 ms.
10 = 64 ms.
11 = 8 ms.
3
OHS2 On-Hook Speed 2.
This bit, in combination with the OHS bit (Register 16) and the SQ[1:0] bits on-hook speeds
specified are measured from the time the OH bit is cleared until loop current equals zero.
OHS OHS2 SQ[1:0] Mean On-Hook Speed
0
0
00
Less than 0.5 ms
0
1
00
3 ms ±10% (meets ETSI standard)
1
X
11
26 ms ±10% (meets Australia spark quenching spec)
4,2 Reserved Read returns zero.
1
FILT Filter Pole Selection (Si3019 line-side device only).
0 = The receive path has a low –3 dBFS corner at 5 Hz.
1 = The receive path has a low –3 dBFS corner at 200 Hz.
0
LVFD Line Voltage Force Disable (Si3019 line-side device only).
0 = Normal operation.
1 = The circuitry that forces the LVS register (Register 29) to all 0s at 3 V or less is disabled.
The LVS register may display unpredictable values at voltages between 0 to 2 V. All 0s are
displayed if the line voltage is 0 V.
74
Rev. 1.02