SMD500 Datasheet, PDF (7/10 Pages) List of Unclassifed Manufacturers – Altimeter / Barometer Module ultra low power, low voltage

4. Serial Interface
The SMD500 has an I²C bus interface comprising of serial clock (SCL) and serial data (SDA). SDA and SCL have open-drain
outputs, so an external pull-up resistor is required, typically 4.7 kΩ. For more information see I²C protocol specification. The I²C
bus is used to control the sensor, read calibration data from the PROM and to read the measured results when A/D conversion is
finished.
The digital interface also includes master clock (MCLK) input and master clear (XCLR) input. The MCLK signal needs to be
clocked during the conversion period. It can be stopped after the A/D conversion has been finished. MCLK can also run
continuously. It must be generated by a crystal oscillator. It can be downscaled by frequency division, but a PLL synthesizer must
not be used because of jitter.
XCLR is used to reset the A/D converter. Reset initializes internal registers and counters. The device is automatically reset by
power on reset (POR) circuitry. If the supply voltage rise time is longer than 400 ns, it is required to reset the device with XCLR
reset. If the supply voltage rise time is shorter, the XCLR reset is not necessary.
4.1 Device and register address
The I2C bus standard makes it possible to connect several I²C bus devices into the same bus. The SMD500 module address is
shown below. The LSB of the device address distinguishes between read (1) and write (0) operation, corresponding to address
0xEF (read) and 0xEE (write).
Table 3: SMD500 device address
A7 A6 A5 A4 A3 A2 A1 W/R
1 1 1 0 1 1 1 0/1
4.2 Definition I²C protocol
The I²C interface definition has special bus signal conditions. Figure 5 shows start (S), stop (P) and binary data conditions.
At start condition SCL is high and SDA has a falling edge. Then the slave address is sent. After the 7 address bits the direction
control bit R/W selects read or write operation. When a slave device recognizes it is being addressed, it should acknowledge by
pulling SDA low in the ninth SCL (ACK) cycle.
At stop condition SCL is also high but SDA has a rising edge. Data must be held stable at SDA when SCL is high. Data can
change value at SDA only when SCL is low.
Figure 5: I²C Interface protocol definition
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