SGU04G72F1BB1SA-BBRT Datasheet, PDF (7/17 Pages) List of Unclassifed Manufacturers – 4096MB DDR3 . SDRAM ECC UDIMM

preliminary Data Sheet
Rev.0.9 17.04.2013
I_DD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C°, VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
Parameter
& Test Condition
max.
Symbol
12800 CL11 10600 CL9
OPERATING CURRENT *) :
One device bank Active-Precharge;
I_DD0
405
360
t_RC= t_RC (I_DD); t_CK = t_CK (I_DD); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT *) :
One device bank; Active-Read-Precharge;
I_DD1
495
450
I_OUT = 0mA; BL = 4, CL = CL (I_DD), AL = 0;
t_CK = t_CK (I_DD), t_RC= t_RC (I_DD), t_RAS = t_RAS MIN (I_DD),
t_RCD = t_RCD (I_DD); CKE is HIGH, CS# is HIGH between valid
commands; Address inputs changing once every two
clock cycles; Data Pattern is same as I_DD4W
PRECHARGE POWER-DOWN CURRENT: Fast Exit
I_DD2P
135
135
All device banks idle; Power-down mode;
t_CK = t_CK (I_DD); CKE is LOW; All Control and
Address bus inputs are not changing; DQ’s
are floating at V_REF
Slow Exit
135
135
Unit
8500 CL7
360
mA
450
mA
135
mA
135
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
I_DD2Q
180
180
180
mA
t_CK = t_CK (I_DD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at V_REF
PRECHARGE STANDBY CURRENT:
All device banks idle;
I_DD2N
225
225
180
mA
t_CK = t_CK (I_DD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
ACTIVE POWER-DOWN CURRENT:
I_DD3P
180
180
180
mA
All device banks open; t_CK = t_CK (I_DD); CKE is LOW; All
Control and Address bus inputs are not changing; DQ’s
are floating at V_REF (always fast exit)
ACTIVE STANDBY CURRENT:
All device banks open; t_CK = t_CK (I_DD),
I_DD3N
270
270
270
mA
t_RAS = t_RAS MAX (I_DD), t_RP = t_RP (I_DD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
OPERATING READ CURRENT:
I_DD4R
900
765
630
mA
All device banks open, Continuous burst reads; One
module rank active; I_OUT = 0mA; BL = 4, CL = CL (I_DD), AL
= 0; t_CK = t_CK (I_DD), t_RAS = t_RAS MAX (I_DD), t_RP = t_RP (I_DD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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