NM9820 Datasheet, PDF (7/18 Pages) List of Unclassifed Manufacturers – Single PCI UART

NetMos
Technology
Nm9820
Single PCI UART
Address phase:
Every PCI transaction starts off with an address phase,
one PCI clock period in duration. During address phase
the initiator (Also known as current bus master)
identifies the target device (via the address) and type
of transaction. (via the Command).The initiator drives
the 32 bit address on to 32 bit Address/Data bus and
4bit command on to 4bit Command / Byte enable bus.
The initiator also asserts the nFRAME signal during
the same clock cycle to indicate the presence of valid
address and transaction type on those buses. The
initiator supplies start address (and the target, Nm9820,
generates the subsequent sequential addresses for
burst transfers) and command type for one PCI clock
cycle. The Address/Data bus becomes Data bus and
Command/Byte enable bus becomes Byte enable bus
for the remainder of the clock cycles of that transaction.
The target (Nm9820) latches the address and
command type on the next rising edge of PCI clock
(and so do all the devices on that PCI bus). The target
(Nm9820) decodes the address and determines
whether it is being addressed, and decodes the
command to determine the type of transaction.
Claiming the transaction:
When Nm9820 determines that it is the target of a
transaction, it claims the transaction by asserting
nDEVSEL.
Transaction duration:
The initiator, as stated earlier, gives only start address
during address phase but does not tell the number of
data transfers in a burst transfer transaction. However
the initiator indicates the completion of data transfer of
a transaction by asserting nIRDY and de-asserting
nFRAME during the last data transfer phase. The
transaction however, does not complete until the target
has also asserted the nTRDY signal and the last data
transfer takes place. At this point the nTRDY and
nDEVSEL are de-asserted by the target.
Transaction completion:
When all of nIRDY, nTRDY, nDEVSEL, and nFRAME
are in inactive state (high state), the bus is in idle state.
The bus is ready to be claimed by another bus master.
Internal address select configuration
I/O Address Function
XX00-XX07 UART (E1)
Data phase(s):
The data phase of a transaction is the period during
which a data object is transferred between the initiator
and the target (Nm9820). The number of data bytes to
be transferred during a data phase is determined by
the number of Command/Byte enable signals that are
asserted by the initiator during the data phase. Each
data phase is at least one PCI clock period in duration.
Both initiator and target must indicate that they are ready
to complete a data phase. If not, the data phase is
extended by a wait state of one clock period in duration.
The initiator and the target indicate this by asserting
nIRDY and nTRDY respectively and the data transfer
is completed at the rising edge of the next PCI clock.
Rev. 1.0
Page 1-39