GDM2004D Datasheet, PDF (7/9 Pages) List of Unclassifed Manufacturers – SPECIFICATIONS OF LCD MODULE

GDM2004D-FL-YBW
8) Set DDRAM address
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Set DDRAM address to AC.
This instruction makes DDRAM data available form MPU.
When 1-line display mode (N=LOW), DDRAM address is form “00H” to “4FH”.
In 2-line display mode (N=High), DDRAM address in the 1^st line form “00H” to “27H”, and DDRAM address
In the 2^nd line is from “40H” to “67H”.
9) Read busy flag & address
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BF
AC6
AC5
AC4
AC3
AC2
AC1
AC0
This instruction shows whether KS0066U is in internal operation or not.
If the resultant BF is “High”, internal operation is in progress and should wait BF is to be LOW, which by then if the nest
instruction can be performed. In this instruction you can also read the value of the address counter.
10) Write data to RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write binary 8-bit data to DDRAM/CGRAM.
The selection of RAM from DDRAM, and CGRAM, is set by the previous address set instruction (DDRAM address set,
CGRAM address set).
RAM set instruction can also determine the AC direction to RAM.
After write operation. The address is automatically increased/decreased by 1, according to the entry mode.
11) Read data from RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8-bit data from DDRAM/CGRAM.
The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not
performed before this instruction, the data that has been read first is invalid, as the direction of AC is not yet determined.
If RAM data is read several times without RAM address instructions set before, read operation, the correct RAM data
can be obtained from the second. But the first data would be incorrect, as there is no time margin to transfer RAM data.
In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction,
It also transfers RAM data to output data register.
After read operation, address counter is automatically increased/decreased by 1 according to the entry mode.
After CGRAM read operation, display shift may not be executed correctly.
NOTE: In case of RAM write operation, AC is increased/decreased by 1 as in read operation.
At this time, AC indicates next address position, but only the previous data can be read by the read instruction.
VER 1.0
7/9
2003/12/09