LM3S610 Datasheet, PDF (64/409 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Table 6-1. System Control Register Map (Continued)
Offset Name
Reset
Type Description
0x034
0x040
0x044
0x048
0x050
0x054
0x058
0x05C
0x060
0x064
LDOPCTL
SRCR0
SRCR1
SRCR2
RIS
IMC
MISC
RESC
RCC
PLLCFG
System Control
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x144
0x150
0x160
RCGC0
RCGC1
RCGC2
SCGC0
SCGC1
SCGC2
DCGC0
DCGC1
DCGC2
DSLPCLKCFG
CLKVCLR
LDOARST
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
-
0x078E3AC0
-
R/W LDO Power Control
R/W Software Reset Control 0
R/W Software Reset Control 1
R/W Software Reset Control 2
RO Raw Interrupt Status
R/W Interrupt Mask Control
R/W1C Masked Interrupt Status and Clear
R/W Reset Cause
R/W Run-Mode Clock Configuration
RO XTAL to PLL translation
0x00000000
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x07800000
0x00000000
0x00000000
R/W Run-Mode Clock Gating Control 0
R/W Run-Mode Clock Gating Control 1
R/W Run-Mode Clock Gating Control 2
R/W Sleep-Mode Clock Gating Control 0
R/W Sleep-Mode Clock Gating Control 1
R/W Sleep-Mode Clock Gating Control 2
R/W Deep-Sleep-Mode Clock Gating Control 0
R/W Deep-Sleep-Mode Clock Gating Control 1
R/W Deep-Sleep-Mode Clock Gating Control 2
R/W Deep-Sleep Clock Configuration
R/W Clock verification clear
R/W Allow unregulated LDO to reset the part
See
page
76
77
78
79
80
81
83
84
85
90
91
93
95
91
93
95
91
93
95
96
97
98
6.4 Register Descriptions
The remainder of this section lists and describes the System Control registers, in numerical order
by address offset.
64
April 27, 2007
Preliminary