HMS87C1808B Datasheet, PDF (64/99 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS87C1X04B/08B/16B
The interrupts are controlled by the interrupt master enable flag
I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL)
and the interrupt request flags (in IRQH, IRQL) except Power-on
reset and software BRK interrupt.
Interrupt enable registers are shown in Figure 16-2 . These regis-
ters are composed of interrupt enable flags of each interrupt
source, these flags determines whether an interrupt will be ac-
cepted or not. When enable flag is “0”, a corresponding interrupt
source is prohibited. Note that PSW contains also a master enable
bit, I-flag, which disables all interrupts at once.
Reset/Interrupt Symbol Priority Vector Addr.
Hardware Reset RESET
-
External Interrupt 0 INT0
1
External Interrupt 1 INT1
2
Timer 0
Timer 0
3
Timer 1
Timer 1
4
External Interrupt 2 INT2
5
External Interrupt 3 INT3
6
Timer 2
Timer 2
7
Timer 3
Timer 3
8
A/D Converter
A/D C
9
Watch Dog Timer WDT
10
Basic Interval Timer BIT
11
Serial Interface
SPI
12
Table 16-1 Interrupt Priority
FFFE_H
FFFA_H
FFF8_H
FFF6_H
FFF4_H
FFF2_H
FFF0_H
FFEE_H
FFEC_H
FFEA_H
FFE8_H
FFE6_H
FFE4_H
IENH
IENL
IRQH
IRQL
Interrupt Enable Register High
INT0E INT1E
T0E
T1E
INT2E INT3E
T2E
T3E
Interrupt Enable Register Low
ADE WDTE BITE
SPIE
-
-
-
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
0 : Disable
1 : Enable
Interrupt Request Register High
INT0IF INT1IF T0IF
T1IF
INT2IF INT3IF
T2IF
-
T3IF
Interrupt Request Register Low
ADIF WDTIF BITIF
SPIF
-
-
-
-
Shows the interrupt occurrence
0 : Not occurred
1 : Interrupt request is occurred
ADDRESS : E2H
RESET VALUE : 0000_0000
ADDRESS : E3H
RESET VALUE : 0000_----
ADDRESS : E4H
RESET VALUE : 0000_0000
ADDRESS : E5H
RESET VALUE : 0000_----
Figure 16-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occurred, the I-flag is cleared and disable
any further interrupt, the return address and PSW are pushed into
the stack and the PC is vectored to. Once in the interrupt service
routine the source(s) of the interrupt can be determined by polling
the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by software be-
fore re-enabling interrupts to avoid recursive interrupts. The In-
terrupt Request flags are able to be read and written.
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SEP. 2004 Ver 1.03