IT8673F Datasheet, PDF (61/128 Pages) List of Unclassifed Manufacturers – Advanced Input / Output (Advanced I/O) Preliminary Specification V0.5

IT8673F
Table 11-6. Data Rate Select Register (DSR)
Bit Symbol
Name
Description
7
S/W
Software Reset Software Reset. It is active high and shares the same function with the
RESET
RESET# of the DOR except that this bit is self-clearing.
6
POWER Power Down When this bit is written with a “1”, the floppy controller is put into manual low
DOWN
power mode. The clocks of the floppy controller and data separator circuits
will be turned off until a software reset or the Data Register or Main Status
Register is accessed.
5
NU
Not Used
-
4-2 PRE-COMP Precompensation These three bits are used to determine the value of write
2-0
Select
precompensation that will be applied to the WDATA# pin. Track 0
is the default starting track number, which can be changed by the
CONFIGURE command for precompensation.
PRE_COMP
111
001
010
011
100
101
110
000
Precompensation Delay
0.0 ns
41.7 ns
83.3 ns
125.0 ns
166.7 ns
208.3 ns
250.0 ns
Default
Default Precompensation Delays
Data Rate Precompensation Delay
1Mbps
41.7 ns
500Kbps
125.0 ns
300Kbps
125.0 ns
250Kbps
125.0 ns
1-0 _DRATE1-0 Data Rate
Select
Bits 1-0
00
01
10
11
Data Transfer Rate
500 Kbps
300 Kbps
250 Kbps (default)
1 Mbps
11.4.8.5 Data Register (FIFO, FDC Base Address + 05h)
This is an 8-bit read/write register. It transfers command information, diskette drive status information, and
the result phase status between the host and the FDC. The FIFO consists of several registers in a stack.
Only one register in the stack is permitted to transfer information or status to the data bus at a time.
Table 11-7. Data Register (FIFO)
Bit Symbol
Name
7-0
Data
Description
Command information, diskette drive status, or result phase status data.
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