US3881 Datasheet, PDF (6/6 Pages) List of Unclassifed Manufacturers – CMOS Low Voltage Hall Effect Latch

US3881
CMOS Low Voltage Hall Effect Latch
Physical Characteristics
1.60
1.40
0.84
0.63
0.48
0.43
4.30
3.90
2.64
2.34
U38 ^*
104
0.20
0.00
45^o
Typical
3.20
2.80
1.75
1.55
UA Package Dimensions
5^o
Typical
45^o
Typical
0.38
Typical
(see note 3)
0.41
0.35
NOTES:
1.) Controlling dimension: mm
15.5
1 2 3 2.) Leads must be free of flash and
14.5
plating voids
3.) Do not bend leads within 1mm
of the lead to package interface.
4.) Package dimensions exclude
molding flash
5.) Tolerance is 0.254mm unless
otherwise specified
1.30
1.24
2.57
2.51
0.41
0.35
UA Hall Plate / Chip Location
2.13
1.87
0.45
0.41
1.53
1.27
Marked
Surface
All Dimensions in millimeters
* MARKING:
Line 1:
1st digit (U)
2nd and 3rd digits (38)
= Supplier (Melexis)
= Series (3880)
Line 2:
1st digit (1)
2nd and 3rd digits(04)
= Year (2001)
= Week of Year
PINOUT:
Pin 1
Pin 2
Pin 3
V_DD
GND
Output
SOT-23 Package Dimensions
(Top View)
0.50
0.35
3
3.00
2.60
3104^*
1.80
1.50
1
2
2.10
1.70
Pin #
0.20
MIN
chip
0.66
0.56
0.25
0.10
3.10
2.70
0.10
0.00
0.90
0.70
1.30
1.00
NOTES:
1. MARKING:
1st Digit (3) = Series (3881)
2nd Digit(1) = Year - 2001
Last Digits (04) = Week of Year
2. PINOUT (See Top View at left):
Pin 1 VDD
Pin 2 Output
Pin 3 GND
3. Controlling dimension: mm.
4. Lead thickness after solder plating will be 0.254
mm maximum.
5. Package dimensions exclude molding flash.
6. The end flash shall not exceed 0.127 mm on each
side of package.
7. Tolerance is +/- 0.254 mm unless otherwise
specified.
SOT-23 Hall Plate /
Chip Location
(Bottom View)
0.95
0.85
1.55
1.45
For the latest version of this document,
Go to our website at:
WWW.melexis.com
Or for additional information
Contact Melexis Direct:
Europe and Japan
USA and rest of the world
E-mail: [e-mail] E-mail: [e-mail]
Phone: [phone]
Phone: [phone]
US3881 CMOS Low Voltage Hall Effect Latch
3901003881 Rev 4.2
7/23/01
Page 6