RDC19220 Datasheet, PDF (6/23 Pages) List of Unclassifed Manufacturers – 16-BIT MONOLITHIC TRACKING RESOLVER (LVDT)-TO-DIGITAL CONVERTERS

4) The BIT output which is active low is activated by an error of
approximately 100 LSBs. During normal operation for step
inputs or on power up, a large error can exist.
5) This device has several high impedance amplifier inputs (+C,
-C, +S, -S, -VCO and -VSUM). These nodes are sensitive to
noise and coupling components should be connected as
close as possible.
-CAP
RDC-19222/4
10uF
+CAP
6) Setup of bandwidth and velocity scaling for the optimized crit-
ically damped case should proceed as follows:
- Select the desired f BW (closed loop) based on overall
system dynamics.
- Select f carrier ≥ 3.5f BW
- Select the applications tracking rate (in accordance with TABLE 3),
and use appropriate values for R SET and R CLK
-
Compute
Rv
=
Tracking
Full Scale Velocity Voltage
Rate (rps) x 2 ^resolution x 50 pF
x
1.25 V
- Compute CBW (pF) =
3.2 x Fs (Hz) x 10⁸
Rv x (f BW)²
- Where Fs = 67 kHz for R CLK = 30 KΩ
100 kHz for R CLK = 20 KΩ
125 kHz for R CLK = 15 KΩ
- Compute RB =
0.9
CBW x f BW
- Compute ^CBW
10
As an example:
Calculate component values for a 16-bit converter with 100Hz
bandwidth, a tracking rate of 10RPS and a full scale velocity
of 4 volts.
- Rv =
4V
10 rps x 2¹⁶ x 50 pF x 1.25 V
= 97655 Ω
-
Compute
CBW
(pF)
=
3.2 x 67 kHz x 10⁸
97655 x 100 Hz²
= 21955 pF
-
Compute
RB
=
21955
x
0.9
10 ^-12
x
100
Hz
= 410 kΩ
(-5c) -5V
(+5c) +5V
.01uF
.01uF
+
+ 47uF
47uF
FIGURE 5. -5V BUILT-IN INVERTER
7) Selecting a f_BW that is too low relative to the maximum appli-
cation tracking rate can create a spin-around condition in
which the converter never settles. The relationship to insure
against spin-around is as follows (TABLE 3):
8) For RDC-19222 & RDC-19224; package’s only.
This version is capable of +5V only operation. It accomplish-
es this with a charge pump technique that inverts the +5V
supply for use as -5V, hence the +5V supply current doubles.
The built-in -5 V inverter can be used by connecting pin 2 to
26, pin 17 to 22, a 10 µF/10 Vdc capacitor from pin 23 (nega-
tive terminal) to pin 25 (positive terminal), and a 47 µF/10 Vdc
capacitor from -5 V to GND. The current drain from the +5 V
supply doubles. No external -5 V supply is needed (SEE FIG-
URE 5).
Note: DDC has software available to perform the previous calcu-
lations. Contact DDC to request software or visit our web-
site at www.ddc-web.com to download software.
When using the -5 V inverter, the max. tracking rate should be
scaled for a velocity output of 3.5 V max. Use the following equa-
tion to determine tracking rate used in the formula on page 5:
TR (required) x (4.0) = Tracking rate used in calculation
(3.5)
TABLE 3. TRACKING/BW RELATIONSHIP
RPS (MAX)/BW
RESOLUTION
1
10
0.45
12
0.25
14
0.125
16
Note: When using the highest BW and Tracking Rates, using
the -5 V inverter is not recommended.
HIGHER TRACKING RATES AND CARRIER FREQUENCIES
Tracking rate (nominally 4 V) is limited by two factors: velocity
voltage saturation and maximum internal clock rate (nominally
1,333,333 Hz). An understanding of their interaction is essential
to extending performance.
Data Device Corporation
www.ddc-web.com
The General Setup Considerations section makes note of the
selection of Rv for the desired velocity scaling. Rv is the input resis-
RDC-19220 SERIES
6
R-12/05-0