IS42S16400B Datasheet, PDF (6/55 Pages) List of Unclassifed Manufacturers – 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

IS42S16400B
ISSI ^®
TRUTH TABLE – COMMANDS AND DQM OPERATION⁽¹⁾
FUNCTION
CS RAS CAS WE DQM
ADDR
DQs
COMMAND INHIBIT (NOP)
H
X
X
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)⁽³⁾
L
L
H
H
X
READ (Select bank/column, start READ burst)⁽⁴⁾
L
H
L
H L/H⁽⁸⁾
WRITE (Select bank/column, start WRITE burst)⁽⁴⁾ L
H
L
L L/H⁽⁸⁾
Bank/Row
Bank/Col
Bank/Col
X
X
Valid
BURST TERMINATE
L
H
H
L
X
PRECHARGE (Deactivate row in bank or banks)⁽⁵⁾ L
L
H
L
X
AUTO REFRESH or SELF REFRESH^(6,7)
L
L
L
H
X
(Enter self refresh mode)
LOAD MODE REGISTER⁽²⁾
L
L
L
L
X
Write Enable/Output Enable⁽⁸⁾
————
L
Write Inhibit/Output High-Z⁽⁸⁾
—
—
—
—
H
X
Code
X
Op-Code
—
—
Active
X
X
X
Active
High-Z
NOTES:
1. CKE is HIGH for all commands except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
auto precharge; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/10/05