IC41C16105 Datasheet, PDF (6/18 Pages) List of Unclassifed Manufacturers – 1M X 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

IC41C16105
IC41LV16105
ELECTRICAL CHARACTERISTICS⁽¹⁾
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
IIL
Input Leakage Current
Any input 0V < VIN < Vcc
Other inputs not under test = 0V
–5
5
µA
IIO
Output Leakage Current
Output is disabled (Hi-Z)
0V < VOUT < Vcc
–5
5
µA
VOH
Output High Voltage Level
IOH = –5.0 mA (5V)
IOH = –2.0 mA (3.3V)
2.4 —
V
VOL
Output Low Voltage Level
IOL = 4.2 mA (5V)
IOL = 2.0 mA (3.3V)
— 0.4
V
ICC1
Standby Current: TTL
RAS, LCAS, UCAS > VIH Commerical 5V
—
3.3V —
Extended & Idustrial 5V —
3.3V —
2
mA
1
3
mA
2
ICC2
Standby Current: CMOS
RAS, LCAS, UCAS > VCC – 0.2V
5V —
3.3V —
1
mA
0.5
ICC3
Operating Current:
RAS, LCAS, UCAS,
Random Read/Write^(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
-50 — 160 mA
-60 — 145
ICC4
Operating Current:
RAS = VIL, LCAS, UCAS,
.ast Page Mode^(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
-50 — 90 mA
-60 — 80
ICC5
Refresh Current:
RAS Cycling, LCAS, UCAS > VIH
RAS-Only^(2,3)
tRC = tRC (min.)
Average Power Supply Current
-50 — 160 mA
-60 — 145
ICC6
Refresh Current:
RAS, LCAS, UCAS Cycling
CBR^(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-50 — 160 mA
-60 — 145
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tRE. refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each .ast page cycle.
5. Enables on-chip refresh and address counters.
S2-6
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001