HMN1288D Datasheet, PDF (6/9 Pages) List of Unclassifed Manufacturers – Non-Volatile SRAM MODULE 1Mbit (128K x 8-Bit), 32Pin-DIP, 5V

HANBit
HMN1288D
POWER-DOWN/POWER-UP CYCLE (T_A= T_OPR, V_CC=5V)
PARAMETER
SYMBOL
CONDITIONS
MIN
V_CC slew, 4.75 to 4.25V
t_PF
300
V_CC slew, 4.75 to V_SO
t_FS
10
V_CC slew, V_SO to V_PFD (max)
t_PU
0
Chip enable recovery time
Data-retention time in
Absence of V_CC
Write-protect time
Time during which SRAM
t_CER
is write-protected after V_CC
40
passes V_PFD on power-up.
t_DR
T_A = 25℃
10
Delay after V_CC slew’s down
t_WPT
past V_PFD before SRAM is
40
Write-protected.
TYP.
-
-
-
80
-
100
MAX
-
-
-
120
-
150
UNIT
㎲
㎲
㎲
ms
years
㎲
TIMING WAVEFORM
- READ CYCLE NO.1 (Address Access)*^1,2
Address
DOUT
tRC
tACC
tOH
Previous Data Valid
Data Valid
- READ CYCLE NO.2 (/CE Access)^*1,3,4
tRC
CE
DOUT
tACE
tCLZ
High-Z
tCHZ
High-Z
URL : www.hbe.co.kr
Rev. 1.0 (June, 2002)
6
HANBit Electronics Co.,Ltd