GS72108ATP Datasheet, PDF (6/12 Pages) List of Unclassifed Manufacturers – 256K x 8 2Mb Asynchronous SRAM

GS72108ATP/J
AC Characteristics
Read Cycle
Parameter
-7
-8
-10
-12
Symbol
Unit
Min Max Min Max Min Max Min Max
Read cycle time
tRC
7
—
8
—
10 — 12 —
ns
Address access time
tAA
—
7
—
8
— 10 — 12
ns
Chip enable access time (CE)
tAC
—
7
—
8
— 10 — 12
ns
Byte enable access time (UB, LB)
tAB
—
3
—
3.5
—
4
—
5
ns
Output enable to output valid (OE)
tOE
—
3
—
3.5
—
4
—
5
ns
Output hold from address change
tOH
3
—
3
—
3
—
3
—
ns
Chip enable to output in low Z (CE)
tLZ^*
3
—
3
—
3
—
3
—
ns
Output enable to output in low Z (OE)
tOLZ^*
0
—
0
—
0
—
0
—
ns
Byte enable to output in low Z (UB, LB) _tBLZ^*
0
—
0
—
0
—
0
—
ns
Chip disable to output in High Z (CE)
tHZ^*
—
3.5
—
4
—
5
—
6
ns
Output disable to output in High Z (OE) _tOHZ^*
—
3
—
3.5
—
4
—
5
ns
* These parameters are sampled and are not 100% tested.
Address
Data Out
Read Cycle 1: CE = OE = V_IL, WE = V_IH
tRC
tAA
tOH
Previous Data
Data valid
Rev: 1.05 10/2004
6/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology