DMR01 Datasheet, PDF (6/13 Pages) List of Unclassifed Manufacturers – Low Power Digital Multichannel Receiver

Datasheet_DMR01 June 2003
Communication via SPI Interface
Each data transfer is initialized with a 8bit control word:
Bit 7
Cmd2
Bit 6
Cmd1
Bit 5
Cmd0
Bit 4
Adr4
Bit 3
Adr3
Bit 2
Adr2
Bit 1
Adr1
Bit 0
Adr0
Cmd2...Cmd0 represent the command word and define the action. Adr4..Adr0 is the address which will be accessed. The following
commands are possible:
Cmd2
0
0
0
0
1
1
1
1
Cmd1
0
0
1
1
0
0
1
1
Cmd0
0
1
0
1
0
1
0
1
Action
Not defined
Read register (address 00 to 07H)
Read YCUML (only for test)
Read YCUMH (only for test)
Read incoming data (address 00 to 11H)
Write register (address 00 to 07H)
Read ZINTL (only for test)
Read ZINTH (only for test)
Each data transfer starts with a command and a corresponding address. Communication is initialized with the falling edge of CS. There is
an auto increment function implemented for read and write operation. This means that the command word is necessary only once for
consecutive addresses.
The MSB (most significant bit, bit7) has to be set first in write operation and will be present first in read operation. Data at ‘Sin’ is sampled
with the positive edge of ‘Sck’ whereas Data at ‘Sout’ will be updated with the negative edge of ‘Sck’.
Bus Timing
Write Sequence
Fig.8 shows the write timing. In this case the
command word is “write register (address 00H)”.
The value which is stored in this register is AAH.
Read Sequence
Fig.9 shows the read timing. In this case the
command word is “read register (address 00H)”.
The value which is clocked at ‘Sout’ is AAH.
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