SI2401 Datasheet, PDF (59/74 Pages) List of Unclassifed Manufacturers – V.22BIS ISOMODEM WITH INTEGRATED GLOBAL DAA

Si2401
SEE (RVC3). Ring Validation Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
RTO[3:0]
RMX[3:0]
Type
R/W
R/W
Reset settings = 0001_0110 (0x16)
Bit
Name
Function
7:4 RTO[3:0] Ring Timeout.
These bits set when a ring signal is determined to be over after the most recent ring
threshold crossing.
RTO[3:0]
Ring Timeout
0000
80 ms
0001
128 ms
0010
256 ms
.
.
.
1111
1920 ms
3:0 RMX[3:0] Ring Assertion Maximum Count.
These bits set the maximum ring frequency for a valid ring signal. During ring qualification,
a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a reg-
ular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the
RMX[3:0] field, and if it exceeds the value in RMX[3:0], the frequency of the ring is too
high, and the ring is invalidated. The difference between RAS[5:0] and RMX[3:0] identifies
the minimum duration between TIP/RING events to qualify as a ring, in binary-coded incre-
ments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period.
At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the cor-
rect RMX[3:0] value for a frequency range [f_min, f_max], the following equation should be
used: RMX[3:0] x 2 ms = RAS[5:0] – 2 ms – (1/(2 x f_max)).
Preliminary Rev. 0.9
59