LM3S6938 Datasheet, PDF (56/516 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
1. The external reset pin (RST) is asserted and then de-asserted.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for
synchronization.
6.1.2.4
The external reset timing is shown in Figure 21-11 on page 490.
Power-On Reset (POR)
The Power-On Reset (POR) circuit monitors the power supply voltage (V_DD). The POR circuit
generates a reset signal to the internal logic when the power supply ramp reaches a threshold value
(V_TH). If the application only uses the POR circuit, the RST input needs to be connected to the power
supply (V_DD) through a pull-up resistor (1K to 10K Ω).
The device must be operating within the specified operating parameters at the point when the on-chip
power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within
10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of
an external reset to hold the device in reset longer than the internal POR, the RST input may be
used with the circuit as shown in Figure 6-1 on page 56.
Figure 6-1. External Circuitry to Extend Reset
D₁
R₁
R₂
C₁
Stellaris
RST
6.1.2.5
The R₁ and C₁ components define the power-on delay. The R₂ resistor mitigates any leakage from
the RST input. The diode (D₁) discharges C₁ rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST) or internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing
is shown in Figure 21-12 on page 491.
Note: The power-on reset also resets the JTAG controller. An external reset does not.
Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (V_DD) drops
below a brown-out threshold voltage (V_BTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
56
October 08, 2007
Preliminary