ACEX1 Datasheet, PDF (56/86 Pages) List of Unclassifed Manufacturers – Programmable Logic Device Family

ACEX 1K Programmable Logic Device Family Data Sheet
Table 24. EAB Timing Microparameters Note (1)
Symbol
t_EABDATA1
t_EABDATA2
t_EABWE1
t_EABWE2
t_EABRE1
t_EABRE2
t_EABCLK
t_EABCO
t_EABBYPASS
t_EABSU
t_EABH
t_EABCLR
t_AA
t_WP
t_RP
t_WDSU
t_WDH
t_WASU
t_WAH
t_RASU
t_RAH
t_WO
t_DD
t_EABOUT
t_EABCH
t_EABCL
Parameter
Data or address delay to EAB for combinatorial input
Data or address delay to EAB for registered input
Write enable delay to EAB for combinatorial input
Write enable delay to EAB for registered input
Read enable delay to EAB for combinatorial input
Read enable delay to EAB for registered input
EAB register clock delay
EAB register clock-to-output delay
Bypass register delay
EAB register setup time before clock
EAB register hold time after clock
EAB register asynchronous clear time to output delay
Address access delay (including the read enable to output delay)
Write pulse width
Read pulse width
Data setup time before falling edge of write pulse
Data hold time after falling edge of write pulse
Address setup time before rising edge of write pulse
Address hold time after falling edge of write pulse
Address setup time before rising edge of read pulse
Address hold time after falling edge of read pulse
Write enable to data output valid delay
Data-in to data-out valid delay
Data-out delay
Clock high time
Clock low time
Conditions
(5)
(5)
(5)
(5)
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