KAC-1310 Datasheet, PDF (55/76 Pages) List of Unclassifed Manufacturers – 1280 (H) x 1024 (V) SXGA CMOS Image Sensor

IMAGE SENSOR SOLUTIONS
IMAGE SENSOR SOLUTIONS
Capture Mode Control (40_h)
The Capture Mode Control Register defines how
the data is captured and how the data is to be
provided at the output. Setting the cms bit will
stop the current CFRS output data stream at the
end of the current frame and place the imager in
Single Frame Capture Mode (SFRS). While the
cms bit is set (SFRS), the output of frames can be
paused with the TRIGGER input pin. When the
TRIGGER pin is low (V_SS) the output of frames is
suspended. When the TRIGGER pin is high (V_DD)
frames are continuous. The default for cms is 0
(CFRS). In CFRS the frames are continuously
output and the TRIGGER pin is ignored. The
Frame Rate is slightly reduced when the cms is
set (SFRS) because care is taken in the startup
such that the first frame output is valid. This
causes a slight delay at the start of each frame.
See Figure 22 on page 32 for a timing diagram for
SFRS mode. With the cms low(=0), the Frame
Rate is faster, but the first frame will be invalid
(wrong integration time).
When the hm bit is set, the HCLK sync is high
whenever valid WOI pixel data is being clocked
out and low during the other blanking intervals.
The HCLK does NOT toggle at the MCLK rate
when the hm bit is set. When hm is set the HCLK
will go high once at the beginning of the valid pixel
data and remain high until the last WOI pixel has
been clocked out. When the hm bit is set the he
bit is ignored. The sp bit is used to define whether
SOF is active high or low. SOF is active high by
default. The ve bit is used to determine whether
VCLK is output at the beginning of the virtual
frame rows or only for the WOI rows. The ve bit
defaults to VCLK on WOI rows only. The vp bit is
used to define whether VCLK is active high(the
default) or active low. The he bit is used to
determine whether HCLK is output continuously
(needed for some frame grabbers) or only for
pixels within the WOI (default). The hp bit is used
to define whether HCLK is active high (default) or
low.
Address
40_h
Capture Mode Control
7 (msb)
6
5
4
3
2
1
FUO
cms
sp
ve
vp
he
hp
Bit
Number
Function Description
7
FUO Factory Use Only
6
RSCM 0_b = Continuous Frame Rolling Shutter (CFRS)
Mode _{1b = Single Frame Rolling Shutter (SFRS)}
5
SOF 0_b = SOF sync active low
Phase 1_b = SOF sync active high
4
VCLK 0_b = VCLK Sync on WOI rows only
Enable 1_b = VCLK Sync on WOI and Virtual Rows
3
VCLK 0_b = Active low
Phase 1_b = Active high
2
HCLK 0_b = Pixel sync on WOI pixels only
Enable 1_b = Continuous pixel sync
1
HCLK 0_b = Active low
Phase 1_b = Active high
0
HCLK 0_b = Toggles - Toggles at MCLK rates defined by (he) bit
Mode 1_b = Continuous - Pixel Valid Envelope
Table 27: Capture Mode Register (40_h)
Default
2A_h
0 (lsb)
hm
Reset
State
0_b
0_b
1_b
0_b
1_b
0_b
1_b
0_b
55
KAC-1310 Rev 4 • www.kodak.com/go/imagers 585-722-4385 Email: [e-mail]