ISP1161A1BMUM Datasheet, PDF (52/137 Pages) List of Unclassifed Manufacturers – As from August 2nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless

Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
10.1.6 HcInterruptDisable register (R/W: 05H/85H)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing a logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
writing a logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned.
Code (Hex): 05 — read
Code (Hex): 85 — write
Table 18: HcInterruptDisable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
MIE
reserved
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00H
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00H
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
RHSC
FNO
UE
RD
SF
reserved
SO
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 19: HcInterruptDisable register: bit description
Bit
Symbol Description
31
MIE
A logic 0 is ignored by the HC. A logic 1 disables interrupt
generation due to events specified in other bits of this register. This
bit is set after a hardware or software reset.
30 to 7
-
reserved
6
RHSC
0 — ignore
1 — disable interrupt generation due to Root Hub Status Change
9397 750 13961
Product data
Rev. 03 — 23 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
51 of 136