DM9102A Datasheet, PDF (51/77 Pages) List of Unclassifed Manufacturers – Single Chip Fast Ethernet NIC controller

Bit 5: FT, Frame Type
It is set to indicate the received frame is the Ethernet-type. It
is reset to indicate the received frame is the EEE802.3- type.
Valid only when ED is set
Bit 4: RWT, Receive Watchdog Time-Out
It is set to indicate receive Watchdog time-out during the
frame reception. CR5<9> will also be set. Valid only when
ED is set.
Bit 3: PLE, Physical Layer Error
It is set to indicate a physical layer error found during the
frame reception.
RDES1: Descriptor Status and Buffer Size
DM9102A
Single Chip Fast Ethernet NIC controller
Bit 2: AE, Alignment Error
It is set to indicate the received frame ends with a non-byte
boundary.
Bit 1: CE, CRC Error
It is set to indicate the received frame ends with a CRC
error. Valid only when ED is set.
Bit 0: FOE, FIFO Overflow Error
This bit is valid for Ending Descriptor is set. (ED = 1). It is set
to indicate a FIFO Overflow error happens during the frame
reception.
31 30 29 28 27 26 25 24 23 22
CE
21 ~ 11
10 ~ 0
Buffer Length
Bit 24: CE, Chain Enable
Must be 1.
Bit 10-0: Buffer Length
Indicates the size of the buffer.
RDES2: Buffer Starting Address
Indicates the physical starting address of buffer. This address must be double word alignment.
31
0
Buffer Address
IRDES3: Next descriptor Address
Indicates the physical starting address of the chained descriptor under the Chain descriptor structure.
This address must be eight word alignment.
31
0
Next descriptor Address
(b). Transmit Descriptor Format
Each transmit descriptor has four double-word content
and may be read or written by the host or by the DM9102A.
The descriptor format is shown below with detailed
description
Final
51
Version: DM9102A-DS-F03
August 28, 2000