VS133-R512 Datasheet, PDF (5/7 Pages) List of Unclassifed Manufacturers – Memory Module

6. Serial Presence Detect (SPD) Data Structure
Byte
No.
Function
0 Defines # of bytes written into serial memory at module manufacturer
1 Total # of bytes of SPD memory device
2 Fundamental memory type (FPM, EDO, SDRAM..)
3 # of row addresses on this assembly
4 # Column Addresses on this assembly
5 # Module Banks on this assembly
6 Data Width of this assembly
7 ... Data Width continuation
8 Voltage interface standard of this assembly
9 SDRAM Cycle time (highest CAS latency)
10 SDRAM Access from Clock (highest CAS latency)
11 DIMM Configuration type (non-parity, ECC)
12 Refresh Rate/Type
13 Primary SDRAM Width
14 Error Checking SDRAM width
15
Minimum Clock Delay
Back to Back Random Column Address
16 Burst Lengths Supported
17 # of Banks on Each SDRAM Device
18 CAS# Latency
19 CS# Latency
20 Write Latency
21 SDRAM Module Attributes
22 SDRAM Device Attributes: General
23 SDRAM Cycle time (2nd highest CAS latency)
24 SDRAM Access from Clock (2nd highest CAS latency)
25 SDRAM Cycle time (3rd highest CAS latency)
26 SDRAM Access from Clock (3rd highest CAS latency)
27 Minimum Row Precharge Time
28 Row Activate to Row Activate Min.
29 RAS to CAS Delay Min
30 Minimum RAS Pulse Width
31 Density of each bank on module
32 Command and Address signal input setup time
33 Command and Address signal input hold time
34 Data signal input setup time
35 Data signal input hold time
36-61 Superset Information (may be used in future)
62 SPD Data Revision Code
63 Checksum for bytes 0-62
64-66
67 Manufacturer’s JEDEC ID code per JEP-108E
68-71
72 Manufacturing Location
73-90 Manufacturer’s Part Number
91-92 Revision Code
93-94 Manufacturing Date
95-98 Assembly Serial Number
99-125 Manufacturer Specific Data
126 Intel specification frequency
127 Intel Specification CAS# Latency support
128+ Unused storage locations
VS133-R512
PDRB-28998-X045-01
Hex
Value
80
08
04
0D
0A
02
48
00
01
75
54
02
82
08
08
01
8F
04
06
01
01
1F
0E
A0
60
00
00
14
0F
14
2D
40
15
08
15
08
00
12
04
7F
83
00
01
20
00
00
00
00
64
87
00
Function Supported
128Bytes
256Bytes
SDR SDRAM
13
10
2Banks
72bits
LVTTL
7.5ns (CL=3)
5.4ns (CL =3)
ECC
7.8µs
x8bit
x8bit
1CLK
Burst Lengths (1,2,4,8,FULL)
4Banks
CAS Latency =2,3
CS Latency =0
WE Latency =0
Registered with PLL
Supports Write1/Read Burst
Supports Precharge All
Supports Auto-Precharge
10ns (CL=2)
6ns (CL=2)
Non Support
Non Support
20ns
15ns
20ns
45ns
256MB
1.5ns
0.8ns
1.5ns
0.8ns
Undefined
Rev 1.2
Checksum
MELCO inc.
Blank
Undefined
Undefined
Undefined
Undefined
100MHz Compatible
Clock=0
CL =2,3
Undefined
(5/7)
Buffalo Technology