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U631H16 Datasheet, PDF (5/12 Pages) List of Unclassifed Manufacturers – SOFTSTORE 2K X 8 NVSRAM
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
Ai
DQi
Output
Previous
Data Valid
1
tcR
Address Valid
2
ta(A) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Output Data
Valid
9
tv(A)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
Ai
E
G
DQi
Output
ICC
1
tcR
Address Valid
High Impedance
ACTIVE
STANDBY
2
ta(A) 3
ta(E)
7
ten(E)
4
ta(G)
8
ten(G)
10
tPU
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
11
tPD
5
tdis(E)
6
tdis(G)
Output Data
Valid
U631H16
No.
Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2 IEC
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
tAVAV tAVAV
tcW
25
35
45
ns
tWLWH
tw(W)
20
30
35
ns
tWLEH tsu(W)
20
30
35
ns
tAVWL tAVEL
tsu(A)
0
0
0
ns
tAVWH tAVEH tsu(A-WH) 20
30
35
ns
tELWH
tsu(E)
20
30
35
ns
tELEH
tw(E)
20
30
35
ns
tDVWH tDVEH
tsu(D)
12
18
20
ns
tWHDX tEHDX
th(D)
0
0
0
ns
tWHAX tEHAX
th(A)
0
0
0
ns
tWLQZ
tdis(W)
10
13
15 ns
tWHQX
ten(W)
5
5
5
ns
December 12, 1997
5