SLGSSTVF16859 Datasheet, PDF (5/11 Pages) List of Unclassifed Manufacturers – DDR 13 to 26 Bit Registered Buffer

SLGSSTVF16859H/V
SLGSSTVF16859H/V DC Electrical Characteristics - ( For PC1600/2100/2700)
T_A = 0 - 70^oC; V_DD = 2.5 +/-0.2V, V_DDQ = 2.5 +/-0.2V; (unless otherwise stated)
SMBL PARAMETERS
CONDITIONS
V_DDQ
MIN TYP MAX
V_IK
V_OH
I_I = -18mA
I_OH = -100µA
2.3V
-1.2
2.3V -2.7V V_DDQ -
0.2
I_OH = -8mA
2.3V 1.95
V_OL
I_OL = 100µA
2.3V -2.7V
0.2
I_OL = 8mA
2.3V
0.35
I_I
All Inputs
V_I = V_DD or GND
2.7V
+5
Standby (Static) RESET = GND
I_{DD Operating (Static) VI = VIH(AC) or VIL(AC),}
RESET = V_DD
2.7V
10
52
Dynamic
RESET = V_DD,
operating
V_I = V_IH(AC) or V_IL(AC),
(clock only)
CLK & CLK switching
75
I_DDD
50% duty cycle
RESET = V_DD,
I_O = 0
2.5V
Dynamic
Operating
V_I = V_IH(AC) or V_IL(AC),
CLK & CLK switching
(per each data _{50% duty cycle. One data}
15
input)
input switching at half
clock frequency, 50%
duty cycle
r_OH Output High
I_OH = -20mA
2.3V-2.7V 7
13.5 20
r_OL Output Low
I_OL = 20mA
2.3V-2.7V 7
13 20
r_O(D) [r_OH - r_OL] each _{IO = 20mA, TA = 25}^o_C
2.5V
4
separate bit
Data Inputs
V_I = V_REF + 310 mV
2.5
3.5
C_i
CLK and CLK V_ICR=1.25V, V_I(PP) = 360mV
2.5V
2.5
3.5
RESET
V_I = V_DD or GND
2.5
3.5
UNITS
V
µA
µA
mA
µΑ/
ΜΗz
µΑ/
clock
MHZ/
data
Ω
Ω
Ω
pF
Silego Technology Inc.
[phone]
PRELIMINARY
5
Data is subject to change.
May 28, 2003