NT6868A Datasheet, PDF (5/14 Pages) List of Unclassifed Manufacturers – Keyboard Controller

NT6868A
Timing Generation
This block generates the system timing and control
signal supplied to CPU and on-chip peripherals. There
are two types of system clock sources: built-in RC
oscillator or external ceramic resonator. Both of them are
mask optional and generate a 4MHz system clock. They
also generates 2MHz for CPU, and 1MHz for base timer.
The following shows the relationship of code type
number and oscillation type.
Oscillator Type
RC OSC
Ceramic Resonator
Code Number
1
3
The following table provides the relationship between
external resistor and RC OSC frequency. (for reference
only)
External Resistor
(KΩ )
39
43
47
56
RC OSC Frequency (MHz)
4.7
4.44
4
3.68
Base Timer
The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by CPU. After reset,
the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any time.
When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a timer
interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and
begin counting at 00H. The timer interval can be programmed from 1 - 256 µsec. The base timer can be enabled by writing
a '0' to ' ENBT ' in the TCON (Timer Control) register. The ENBT is a level trigger.
Base timer structure:
1µs
8-Bit timer
BT7 BT6 BT5 BT4 BT2 BT2 BT1 BT0
TMRINT
BT pre-load data:
Addr.
Bit
$00C0 BT
Timer Control Regisrer:
7
6
5
4
3
2
1
0
BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0 (W)
$00C1 TCON
-
-
-
-
-
-
-
ENBT ^(W)
INT. Controller
When BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by
software. Once set by an interrupt source, it remains High unless cleared by writing '1' to the corresponding bit in
CLRIRQX ($00C2H). This register is cleared to '0' on initialization by system reset.
When an interrupt occurs, CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine. When BASE TIMER
interrupt occurs and enters the interrupt service routine, the IRQTMR flag must be cleared by software.
Interrupt Control Register:
Addr.
$00C2
Bit
7654321
0
CLRIRQX -
-
-
-
-
-
- CLRIRQTMR (W)
5