MTV016 Datasheet, PDF (5/11 Pages) List of Unclassifed Manufacturers – Enhanced On-Screen-Display Controller

MYSON
TECHNOLOGY
MTV016
character line displays is shown in Tables 2 and 3. The programmable vertical size range is 180 lines to
a maximum of 1420 lines.
The vertical display center for a full screen display may be figured out according to the information of the
vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the leading
edge of VFLB is calculated using the following equation:
vertical delay time = (VERTD * 4 + 1) * H
H = one horizontal line display time
Table 2. Repeat Line Weight of Character
CH6 - CH0
Repeat Line Weight
CH6,CH5=11
+18*3
CH6,CH5=10
+18*2
CH6,CH5=0x
+18
CH4=1
+16
CH3=1
+8
CH2=1
+4
CH1=1
+2
CH0=1
+1
Table 3. Repeat Line Number of Character
Repeat Line
Repeat Line #
Weight
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+1
- - - - - - - -v- - - - - - - - -
+2
- - - -v- - - - - - -v- - - - -
+4
- -v- - -v- - -v- - -v- - -
+8
-v-v-v-v-v-v-v-v- -
+16
- vvvvvvvvvvvvvvvv -
+17
vvvvvvvvvvvvvvvvv -
+18
vvvvvvvvvvvvvvvvvv
Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the character would not be
repeated.
3.4 Horizontal Display Control
The horizontal display control is used to generate control timing for horizontal displays based on double
character width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR)
and HFLB input. A horizontal display line consists of (HORR*12) dots, including 288 dots for 24 display
characters; the remaining dots are for a blank region. The horizontal delay starting from the HFLB
leading edge is calculated using the following equation:
horizontal delay time = (HORD * 6 + 49) * P - phase error detection pulse width
P = one pixel display time = one horizontal line display time / (HORR*12)
3.5 Phase Lock Loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution
register (HORR). The frequency of VCLK is determined using the following equation:
VCLK Freq = HFLB Freq * HORR * 12
The VCLK frequency ranges from 5MHz to 90MHz and is selected by VCO1and VCO0. In addition,
when HFLB input is not present for MTV016, the PLL will generate a specific system clock,
approximately 2.5MHz, by a built-in oscillator to ensure data integrity.
3.6 Display & Row Control Registers
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MTV016 Revision 2.0 01/01/1999