FS401 Datasheet, PDF (5/104 Pages) List of Unclassifed Manufacturers – PC to TV Video Scan Converters

1. Architectural Overview
Overall design principles are included in this section. Details of how to use and setup the FS400 are included in
the Functional Description section, starting on page 75.
RGB video inputs are asynchronously converted to either NTSC/PAL, YUV or RGB video formats. Architecturally,
the FS400 is divided into five major sections:
1. Video Capture Engine
2. Clock Processor
3. Frame Store Controller
4. Video Encoder Engine
5. Serial Bus Interface
Besides power and a few external passive components, the FS400 requires only a single 16M external SDRAM
and external clocks to implement a high quality video scan converter.
Either analog or digital inputs (FS403 only) with separate horizontal and vertical sync signals are accepted.
Analog VGA video must be RGB. Digital video (FS403 only) must be 24-bit RGB clocked by external clock,
VGACK_IN.
A wide range of resolution formats can be accepted, including common standards such as 320x240, 640x400,
720x400, 640x480, 800x600, 832x624, 1024x768, 1152x864, 1280x1024, and 1600x1200. Incoming RGB
signals are converted to either the NTSC or PAL TV Standards, 100Hz PAL, or progressive scan VGA, SVGA, or
NTSC. Output video format can be selected to be either composite and Y/C (NTSC and PAL only), or RGB or
YUV (all standards).
Incoming frame rate may range to over 150 Hz according to the table below. The Video Capture engine runs
asynchronously relative to the Video Encoder Engine. An external frame store memory separates the two
engines with write and read access controlled by the FS400.
Transformation operations include overscan, underscan, pan and zoom. Scaling operations are separated by the
frame store with vertical down-sampling incorporated into the Capture Engine and horizontal up-sampling
incorporated into the Encoder Engine.
1.1 Video Capture Engine
Triple 8-bit A/D converters digitize the analog RGB inputs at rates of up to 50 MHz. Internal A/D sample clock,
ADCK is derived from a phase locked loop referenced to the leading edge of horizontal sync. Either positive or
negative sync polarity is accepted.
The selected input (A/D converter outputs or digital RGB) is transcoded by the color matrix into a 16-bit YC_RC_B
4:2:2 format. A vertical scaler filters the number of incoming video lines by the selected scaling factor. A flicker
filter averages lines to eliminate flicker between lines or boundaries.
The Video Capture Engine is programmable as to the number of horizontal samples it takes. The limiting factor in
the sample rate is the A/D Converters. By programming fewer samples per line, higher incoming data rates can
be accommodated. The following table illustrates the capability:
Active Samples
Maximum Line Frequency
640 x 480
800 x 600
1024 x 768
1152 x 864
1280 x 1024
1600 x 1200
720 CCIR 601
56kHz
106Hz
89Hz
70Hz
59Hz
53Hz
44Hz
640
63kHz
119Hz
100Hz
78Hz
66Hz
59Hz
50Hz
500
80kHz
152Hz
128Hz
100Hz
85Hz
76Hz
64Hz
JANUARY 24, 2007
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