EN27LV020 Datasheet, PDF (5/13 Pages) List of Unclassifed Manufacturers – 2Megabit Low Voltage EPROM (256K x 8)

EN27LV020 / EN27LV020B
READ MODE
The EN27LV020 / EN27LV020B has two control functions, both of which must be logically
satisfied in order to obtain data at the outputs. Chip Enable ( CE ) is the power control and
should be used for device selection. Output Enable ( OE ) is the output control and should be
used to gate data to the output pins, independent of device selection. Assuming that
addresses are stable, address access time (t_ACC) is equal to the delay from CE to output
(t_CE). Data is available at the outputs (t_OE) after the falling edge of OE , assuming the CE
has been LOW and addresses have been stable for at least t_ACC - t_OE.
STANDBY MODE
The EN27LV020 / EN27LV020B has CMOS standby mode which reduces the maximum V_CC
current to 10µA. It is placed in CMOS standby when CE is at V_CC ± 0.3 V. The EN27LV020
/ EN27LV020B also has a TTL-standby mode which reduces the maximum V_CC current to 0.6
mA. It is placed in TTL-standby when CE is at V_IH. When in standby mode, the outputs are
in a high-impedance state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-line control function is provided to
allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that CE be decoded and used as the primary device-selection function,
while OE be made a common connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all deselected memory devices are in
their low-power standby mode and that the output pins are only active when data is desired
from a particular memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced
on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks
is dependent on the output capacitance loading of the device. At a minimum, a 0.1µF ceramic
capacitor (high frequency, low inherent inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused
by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7µF bulk
electrolytic capacitor should be used between V_CC and V_SS for each eight devices. The location
of the capacitor should be close to where the power supply is connected to the array.
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Preliminary
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