GM2121 Datasheet, PDF (48/51 Pages) List of Unclassifed Manufacturers – SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter

gm2121 Preliminary Data Sheet
5.2 Preliminary AC Characteristics
The following targeted specifications have been derived by simulation.
All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum operating
conditions used were: T_DIE = 0 to 125° C, Vdd = 2.35 to 2.65V, Process = best to worst, C_L = 16pF for all outputs.
Table 21. Maximum Speed of Operation
Clock Domain
Main Input Clock (TCLK)
ADC Clock (ACLK)
HCLK Host Interface Clock (6-wire protocol)
Input Format Measurement Clock (IFM_CLK)
Reference Clock (RCLK)
On-Chip Microcontroller Clock (OCM_CLK)
Display Clock (DCLK)
Max Speed of Operation
24 MHz ( 20.0MHz recommended)
162.5MHz
5 MHz
50MHz ( 20.0MHz recommended)
200MHz (200MHz recommended)
100 MHz
135 MHz
Table 22. Display Timing and DCLK Adjustments
DP_TIMING ->
Propagation delay from DCLK to DA*/DB*
Propagation delay from DCLK to DHS
Propagation delay from DCLK to DVS
Propagation delay from DCLK to DEN
Tap 0 (default)
Min Max
(ns) (ns)
1.0 4.5
1.0 4.5
0.5 4.5
1.0 4.5
Tap 1
Min Max
(ns) (ns)
0.5 3.5
0.5 3.5
0.0 3.5
0.5 3.5
Tap 2
Min Max
(ns) (ns)
-0.5 2.5
-0.5 2.5
-1.0 2.5
-0.5 2.5
Tap 3
Min Max
(ns) (ns)
-1.5 1.5
-1.5 1.5
-2.0 1.5
-1.5 1.5
Note: DCLK Clock Adjustments are the amount of additional delay that can be inserted in the DCLK path, in order to reduce the
propagation delay between DCLK and its related signals.
Table 23. 2-Wire Host Interface Port Timing
Parameter
Symbol
MIN TYP MAX
SCL HIGH time
SCL LOW time
SDA to SCL Setup
SDA from SCL Hold
Propagation delay from SCL to SDA
T_SHI
1.25
T_SLO
1.25
T_SDIS
30
T_SDIH
20
T_SDO3
10
150
Note: The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) (ie 10ns / clock)
Units
us
us
ns
ns
ns
C2121-DAT-01F
48
http://www.genesis-microchip.com
December 2002