LM3S8738 Datasheet, PDF (452/545 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
Register 6: Ethernet MAC Data (MACDATA), offset 0x010
This register enables software to access the TX and RX FIFOs.
Reads from this register return the data stored in the RX FIFO from the location indicated by the
read pointer.
Writes to this register store the data in the TX FIFO at the location indicated by the write pointer.
The write pointer is then auto-incremented to the next TX FIFO location.
There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be
read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has
been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO
sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset
to the start of the TX FIFO by writing the TXER bit of the MACIACK register and the data re-written.
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RXDATA
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RXDATA
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
RXDATA
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
Type
W
W
W
W
Reset
0
0
0
0
15
14
13
12
Type
W
W
W
W
Reset
0
0
0
0
Type
R
Reset
0x0
Description
The RXDATA bits represent the next four bytes of data stored in the RX
FIFO.
27
26
25
24
23
22
21
20
19
18
17
16
TXDATA
W
W
W
W
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
TXDATA
W
W
W
W
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
TXDATA
Type
W
Reset
0x0
Description
The TXDATA bits represent the next four bytes of data to place in the
TX FIFO for transmission.
452
June 14, 2007
Luminary Micro Confidential-Advance Product Information