VPX3220A Datasheet, PDF (41/80 Pages) List of Unclassifed Manufacturers – Video Pixel Decoders

PRELIMINARY DATA SHEET
VPX 3220 A, VPX 216 B, VPX 3214 C
4.9. Initial Values on Reset
PIXCLK LOW on Reset
Type
I²C
I²C
I²C
I²C
I²C
I²C
I²C
I²C
I²C
I²C
I²C
I²C
Name
Address
OFIFO
F0
AFEND
33
IFC
20
YMAX
E0
YMIN
E1
UMAX
E2
UMIN
E3
VMAX
E4
VMIN
E5
CBM_BRI
E6
CBM_CON
E7
FORMAT
E8
Data
0A
0D
03
FF
00
7F
80
7F
80
00
20
F8
I²C
OMUX
F1
00
I²C
DRIVER_A
F8
12
I²C
DRIVER_B
F9
24
I²C
OENA
F2
00
PIXCLK HIGH on Reset
I²C
OFIFO
F0
0B
I²C
AFEND
33
0D
I²C
IFC
20
03
I²C
YMAX
E0
FF
I²C
YMIN
E1
00
I²C
UMAX
E2
7F
I²C
UMIN
E3
80
I²C
VMAX
E4
7F
I²C
VMIN
E5
80
I²C
CBM_BRI
E6
00
I²C
CBM_CON
E7
20
I²C
FORMAT
E8
F8
I²C
OMUX
F1
08
I²C
DRIVER_A
F8
12
I²C
DRIVER_B
F9
24
I²C
OENA
F2
5F
Table of Initial Values
Description
Half full level to 0A_hex (10_dec), bus shuffler off
Video input 2, chroma ADC from Chroma input, clamp off for chroma ADC
IF compensation 0 dB/oct
Open up all comparators, so that Alpha Key is always true (set)
Brightness to 0
Contrast to 1.0, noise shaping 9 to 8 bit via 1 bit rounding
YUV 422, C_r,C_b in binary offset, con/bri clamp to 16_dec, Gamma dither enabled, Alpha
active low, Alpha median filter enabled
single clock, PIXCLK input, posedge triggered, HLEN counter disabled
Port A, PIXCLK, HF# and FE# strength to 2
Port B, HREF, VREF, PREF and ALPHA strength to 4
All outputs disabled
Half full level to 0B_hex (11_dec), bus shuffler off
Video input 2, chroma ADC from Chroma input, clamp off for chroma ADC
IF compensation 0 dB/oct
Open up all comparators, so that Alpha Key is always true (set)
Brightness to 0
Contrast to 1.0, noise shaping 9- to 8-bit via 1-bit rounding
YUV 422, C_r,C_b in binary offset, con/bri clamp to 16_dec, Gamma dither enabled, Alpha
active low, Alpha median filter enabled
single clock, PIXCLK output, HLEN counter disabled
Port A, PIXCLK, HF# and FE# strength to 2
Port B, HREF, VREF, PREF and ALPHA strength to 4
All outputs enabled: synchronize HREF, VREF with PIXCLK
MICRONAS INTERMETALL
41